View CPS1027-S_1915061.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet january 2002 csp1027 voice band codec for cellular handset and modem applications 1 features n d - s (delta-sigma) a/d and d/a converters with stan- dard 16-bit serial i/o interface. n on-chip filters meet itu-t g.712 voice band fre- quency response and signal to distortion plus noise specifications. suitable for is-54, gsm, and jdc digital cellular applications. n low-profile package (<1.5 mm) 48-pin thin quad flat pack (tqfp) available or 44-pin eiaj quad flat pack (qfp). n operates in systems with a 3.0 v to 5.0 v digital power supply and a 5.0 v analog supply. n low-power 0.9 m cmos technology, fully static design, typical power of 68 mw when active and 0.05 mw in standby with a 3.3 v digital supply and a 5.0 v analog supply. n a low-power inactive (standby) state without stop- ping clock or removing power supply. n sampling rates up to 24 khz. n on-chip programmable sampling clock generator allows input clock to be an integer multiple of 125 times the sampling rate or an integer multiple of the sampling rate. n programmable phase adjust of both codec sampling clock and baseband codec clock. n two on-chip clock dividers for generating the output clock for the baseband codec and the output clock for other processors. n regulated microphone power supply. n microphone preamplifier, with programmable input ranges of 0.16 vp-p and 0.5 vp-p. n output amplifier, with programmable gain settings, 0 db to C45 db in C3 db steps. n high-pass filters selectable via control registers. n power-on reset pulse generator. n standard 16-bit serial i/o interface. n serial i/o multiprocessor mode compatible with agere system inc.s dsp16a and dsp1610/1616/1617/1618 digital signal processors. 2 description the agere csp1027 is a high-precision linear voice band d - s (delta-sigma) codec designed for cellular handset and modem applications. the device is fabri- cated in low-power cmos technology and designed for low-voltage (3.0 v to 5.0 v) digital systems. the csp1027 is packaged in a 44-pin eiaj quad flat pack (qfp) or a 48-pin eiaj thin quad flat pack (tqfp). in the 48-pin tqfp, the csp1027 occupies a total volume of 0.0784 cm 3 . the csp1027 has a variety of significant programmable features not found in standard voice band codecs. the analog interface includes a microphone preamplifier with programmable gain settings, an output amplifier with gain programmable in 3 db steps over a 45 db range, and a regulated microphone power supply. an inactive mode allows a low-power standby state, and a mute function provides suppression of the analog output. on- chip antialiasing and anti-imaging filtering includes a selectable high-pass filter. the csp1027 meets itu-t g.712 voice band specifications. the programmable features of the csp1027 are set by writing four on-chip control registers through the serial i/o interface. the codecs digital input/output uses a lin- ear 16-bit twos complement data format that is also transferred through the serial i/o interface. the csp1027 interfaces easily to the 16-bit serial ports of digital signal processors and other devices. the serial interface supports the agere fixed-point dsp family serial multiprocessor mode. this allows up to eight com- patible devices, including two csp1027s, to interface to each other on a common 4-wire bus using a time-divi- sion-multiplexing scheme.
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 2 table of contents contents page 1 features ...................................................................................................................... ................................ 1 2 description ................................................................................................................... ............................... 1 3 pin information .............................................................................................................. ............................. 3 4 architectural information .................................................................................................... ........................ 5 4.1 overview.................................................................................................................... ....................... 6 4.2 description of signal paths................................................................................................. .............. 6 4.3 programmable features ....................................................................................................... .......... 13 4.4 power-on reset .............................................................................................................. ............... 14 4.5 clock generation ............................................................................................................ ................ 16 4.6 serial i/o configurations................................................................................................... .............. 20 5 register information.......................................................................................................... ........................ 26 5.1 codec i/o control 0 ( cioc0 ) register ............................................................................................. 26 5.2 codec i/o control 1 ( cioc1 ) register ............................................................................................. 27 5.3 codec i/o control 2 ( cioc2 ) register ............................................................................................. 28 5.4 codec i/o control 3 ( cioc3 ) register ............................................................................................. 29 6 signal descriptions ........................................................................................................... ........................ 30 6.1 clock interface............................................................................................................. ................... 30 6.2 reset interface ............................................................................................................. .................. 31 6.3 serial i/o interface........................................................................................................ .................. 31 6.4 external gain control interface ............................................................................................. ......... 32 6.5 digital power and ground.................................................................................................... ........... 32 6.6 analog interface............................................................................................................ .................. 32 6.7 analog power and ground ..................................................................................................... ........ 32 7 application information ....................................................................................................... ...................... 33 7.1 analog information.......................................................................................................... ................ 33 7.2 power supply configuration .................................................................................................. ......... 36 7.3 the need for fully synchronous operation ................................................................................... 36 7.4 crystal oscillator.......................................................................................................... ................... 38 7.5 programmable clock generation ............................................................................................... .... 45 8 device characteristics ........................................................................................................ ...................... 47 8.1 absolute maximum ratings .................................................................................................... ........ 47 8.2 handling precautions........................................................................................................ .............. 47 8.3 recommended operating conditions............................................................................................ . 47 9 electrical characteristics and requirements ................................................................................... ......... 48 9.1 power dissipation ........................................................................................................... ................ 50 10 analog characteristics and requirements...................................................................................... .......... 51 10.1 analog input and microphone regulator ...................................................................................... .. 51 10.2 analog-to-digital path..................................................................................................... ................ 52 10.3 digital-to-analog path..................................................................................................... ................ 53 10.4 miscellaneous .............................................................................................................. ................... 54 11 timing characteristics and requirements ...................................................................................... .......... 55 11.1 clock generation ........................................................................................................... ................. 56 11.2 power-on reset ............................................................................................................. ................ 57 11.3 reset ...................................................................................................................... ........................ 58 11.4 serial i/o communication .................................................................................................. ............ 59 11.5 serial multiprocessor communication ........................................................................................ .... 61 12 outline diagrams ............................................................................................................. ......................... 62 12.1 44-pin eiaj quad flat pack (qfp) ........................................................................................... ..... 62 12.2 48-pin eiaj thin quad flat pack (tqfp) ..................................................................................... . 63
agere systems inc. 3 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 3 pin information figure 1. 44-pin eiaj quad flat pack (qfp) pin diagram figure 2. 48-pin eiaj thin quad flat pack (tqfp) pin diagram 1 3 4 5 6 7 8 9 10 11 2 44 42 41 40 39 38 37 36 35 34 43 12 14 15 16 17 18 19 20 21 22 13 33 31 30 29 28 27 26 25 24 23 32 smode2 porb porcap res res res res res smode1 res res res res res res res res smode0 rstb v dda micin v ssa aoutp refc auxin res aoutn v dda v reg v ssa eigs iock cko1 cps1027-j 44-pin qfp xlo xhi sync v dd do sadd clk cko2 xoscen di v ss 5-7567 (f) res res res smode1 smode0 res res res res res res 1 2 3 4 5 6 7 8 9 10 11 cko1 12 36 35 34 33 32 31 30 29 28 27 26 eigs smode2 porcap porb rstb res res res res res res 25 iock clk xlo xhi xoscen cko2 v ss sadd di do v dd res 13 14 15 16 17 18 19 20 21 22 23 sync 24 48 47 46 45 44 43 42 41 40 39 38 v dda auxin refc micin v ssa aoutp res aoutn v dda v reg v ssa 37 res csp1027-s 48-pin tqfp 5-7568 (f)
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 4 3 pin information (continued) functional descriptions of the pins are found in section 6 on page 30. table 1. pin descriptions qfp pin tqfp pin symbol type name/function 1, 2, 3 1, 2, 3 res nc* reserved. 4 4 smode1 i serial mode select 1. 5 5 smode0 i serial mode select 0. 6, 7, 8, 9, 10 6, 7, 8, 9, 10, 11 res nc* reserved. 11 12 cko1 o clock output 1. 12 13 clk i clock input. 13 14 xlo i crystal input. 14 15 xhi o crystal output. 15 16 xoscen i crystal oscillator enable. 16 17 cko2 o clock output 2. 17 18 v ss p digital ground. 18 19 sadd i/o ? serial address. 19 20 di i serial input data. 20 21 do o ? serial output data. 21 22 v dd p digital power supply. 23 res nc* reserved. 22 24 sync i/o ? serial input/output load strobe and synchronization. 23 25 iock i ? serial clock. 24, 25, 26, 27, 28 26, 27, 28, 29, 30, 31 res nc* reserved. 29 32 rstb i reset. 30 33 porb o power-on reset output. 31 34 porcap i external capacitor connection for power-on reset. 32 35 smode2 i serial mode select 2. 33 36 eigs i ** external input gain select. 37 res nc* reserved. 34 38 v ssa p analog ground. 35 39 v reg a regulated output voltage for electrect condenser microphone. 36 40 v dda p analog 5.0 v power supply. 37 41 aoutn a inverting analog output of output amplifier. 38 42 res nc* reserved. 39 43 aoutp a noninverting analog output of output amplifier. 40 44 v ssa p analog ground. 41 45 micin a analog input for microphone. 42 46 refc a external capacitor connection for internal voltage regulator. 43 47 auxin a analog input from auxiliary. 44 48 v dda p analog 5.0 v power supply. * indicates no connection. ? indicates 3-state output. ? indicates pull-up device on input. indicates pull-up resistor on input. ** indicates pull-down device on input.
agere systems inc. 5 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 4 architectural information figure 3. csp1027 block diagram 5-7559 (f) iir low-pass clock generation clk xlo xhi cko1 cko2 cdiv0 (cioc1), cdiv1 (cioc1), cdiv2 (cioc0), cdiv3 (cioc2), cdif0 (cioc2), cdif1 (cioc3), cdif2 (cioc3) 1 mhz oversampling clock on-chip voltage reference circuits v reg (3.0 v) refc a/d input block mic aux insel cioc0 irsel cioc0 a/d test cioc0 sync-cubic digital decimation filter 7th-order iir low-pass filter 3rd-order iir high-pass filter c d x (a/d) do status sio control 1/125 1 mhz oversampling clock 8 khz iock sync sadd smode2 smode1 smode0 hpfe cioc3 m u x digital modulator and gain adjust d/a analog low-pass filter (35 khz) output amp aoutp aoutn sample/hold and 7th-order filter 3rd-order iir high-pass filter c d x (a/d) i s r di c i o c 3 c i o c 2 c i o c 1 c i o c 0 power-on reset porcap porb rstb tstpor cioc3 m u x m u t e m u x m u x o s r m u x test cioc0 dither cioc3 ogsel cioc0 hpfe cioc3 mute cioc0 internal reset eigs xoscen
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 6 4 architectural information (continued) 4.1 overview the csp1027 is a complete analog-to-digital and digi- tal-to-analog acquisition and conversion system (see figure 3 on page 5) that band limits and encodes ana- log input signals into 16-bit pcm, and takes 16-bit pcm inputs and reconstructs and filters the resultant analog output signal. the selectable a/d input circuits, pro- grammable sample rates, and digital filter options allow the user to optimize the codec configuration for either speech coding or voice band data communications. the on-chip digital filters meet the itu-t g.712 voice band frequency response and signal to distortion plus noise specifications and are suitable for is-54, gsm, and jdc digital cellular applications. in addition, the small supply current drain, when powered down, extends battery life in mobile communication applica- tions. the csp1027 is intended for both voice band voice and data communication systems. as a result, this codec has a variety of features not found in standard voice band codecs: n 3.0 v regulated power supply for a condenser micro- phone. n microphone preamplifier with programmable input ranges. n mute control of d/a output. n programmable output gain in 3 db increments. n output speaker driver. n programmable master clock divider to set a/d and d/a conversion rate. n testability loopback mode. n high-quality dither scheme to eliminate idle channel tones. 4.2 description of signal paths 4.2.1 sampling frequency the oversampling ratio of the codec is 125:1; this is the ratio of the frequency of the oversampling clock to the frequency of the sampling clock. most speech applica- tions specify a sampling frequency of 8 khz, yielding an oversampling frequency of 8 khz x 125 = 1.0 mhz. the codec will operate at sampling frequencies up to 24 khz, with the frequency response of the digital filters being changed proportionally. for this architectural description, the sampling frequency, f s , is assumed to be 8 khz, with an oversampling frequency, f os , of 1 mhz, unless otherwise stated. 4.2.2 analog-to-digital path the analog-to-digital (a/d) conversion signal path (see figure 3 on page 5) begins with the analog input driving the input block. the signal from the input block is then encoded by a second-order d - s modulator a/d. the bulk of the antialiasing filtering is done in the digital domain in two stages following the d - s modulator to give a 16-bit result. the blocks will next be covered in more detail. 4.2.3 analog input block the a/d input block operates in two modes: when the external input gain select (eigs) pin is low or left unconnected, the input goes through a preamplifier and is band limited by a second-order 30 khz low-pass anti- aliasing filter (see figure 4 on page 7). when eigs is high, external resistors, rin and rfb, are used to set the gain of an inverting amplifier (see figure 5 on page 7). these resistors, in combination with cin and cfb, cre- ate a bandpass antialiasing filter. note that eigs is a digital pin whose input levels are relative to digital power and ground (v dd and v ss ). 4.2.4 a/d modulator and digital filters a second-order d - s modulator quantizes the analog signal to 1 bit (see figure 3 on page 5). at the same time, the resulting quantization noise is shaped such that most of this noise lies outside of the baseband. the modulator output is then digitally low-pass filtered to remove the out-of-band quantization noise. after this filtering, the output samples are decimated down to the output sampling frequency. in the csp1027, the filter- ing and decimation are completed in two stages. the first-stage low-pass filter shapes the modulator output according to the sinc-cubic transfer function: the output sampling frequency of the sinc-cubic filter is reduced by a factor of 25 from 1 mhz to 40 khz. the sinc-cubic filter places nulls in the frequency response at multiples of 40 khz, and removes most of the quanti- zation noise above 20 khz so that very little energy is aliased as a result of the decimation. the sinc-cubic filter output is then processed by a seventh-order iir digital low-pass filter. this filter removes the out-of-band quantization noise between 3.4 khz and 20 khz, compensates for the passband droop caused by the sinc-cubic decimator, and deci- mates the sampling frequency by a factor of five from 40 khz to 8 khz. hz () 1 25 ------ 1z 25 C C () 1z 1 C C () ------------------------ - 3 =
agere systems inc. 7 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 4 architectural information (continued) following the low-pass filtering and decimation to 8 khz, the 16-bit two's complement pcm can go directly to the output register, cdx(a/d) , or go to a third-order iir digital high-pass filter and then to the output register. the C3 db corner frequency of the high-pass filter is approximately 270 hz. this filter exceeds the vselp preprocessing requirements of is-54 for attenuation of 60 hz and 120 hz signals. the high-pass filter is selected by writing the hpfe field in the cioc3 register (see table 10 on page 29). the default value upon reset is the high-pass filter enabled (hpfe = 0). figure 4. csp1027 a/d path when in the preamplifier mode (eigs = 0) figure 5. csp1027 a/d path in the external gain select mode (eigs = 1) 4.2.5 a/d path frequency response the composite digital filters (decimator, lpf, and hpf) meet the itu-t g.712 voice band frequency response specifications and are suitable for is-54, jdc, and gsm digital cellular applications. figures 6 through 9 show the a/d and d/a frequency response without the optional high-pass filter (hpf). figures 10 and 11 show the group delay characteristics of the a/d and d/a with- out the high-pass filter. figures 12 and 13 show the fre- quency response of the high-pass filter. figures 14 and 15 show the group delay characteristics of the high- pass filter. in all figures, the frequency is normalized to the sampling frequency f s (i.e., frequency/f s ). to get the actual frequency, multiply the normalized frequency by f s . the absolute delay and delay distortion have been normalized to the sampling period 1/f s (i.e., delay x f s ). to obtain the actual delay, divide the normalized delay by f s . the templates shown in figures 7 through 9, 11 through 13, and 15 correspond to the limits in the itu-t g.712 specification where f s = 8.0 khz. 4.2.6 pcm saturation versus analog input levels 16-bit two's complement saturation is employed to pre- vent wraparound during input overload conditions. the saturation is hard-limiting: 0x7fff = maximum positive level 0x8000 = minimum negative level the analog levels that correspond to the saturation lev- els for the three input modes are outlined in table 14 on page 51. micin preamplifier and aa-filter a/d and filters + C rin cin vin1 auxin rin cin vin2 external components 5-7592 (f) micin a/d and filters + C rfb cfb auxin external components internal signal gnd internal signal gnd rin cin C + 5-7593 (f)
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 8 4 architectural information (continued) figure 6. a/d or d/a path frequency response over 5.0 f s bandwidth (hpf disabled) figure 7. a/d or d/a path frequency response over 2.5 f s bandwidth (hpf disabled) 20 0 C20 C120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 frequency (fs = 1) log magnitude (db) C40 C80 C60 C100 5-7594 (f) 5-7595 (f) 10 0 C20 C80 0.0 0.5 1.0 1.5 2.0 2.5 frequency (fs = 1) log magnitude (db) C40 C60 C10 C30 C50 C70
agere systems inc. 9 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 4 architectural information (continued) figure 8. a/d or d/a path frequency response over f s bandwidth (hpf disabled) figure 9. a/d or d/a path frequency response over 0.5 f s bandwidth (hpf disabled) 5-7596 ( f ) 10 0 C20 C80 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (fs = 1) log magnitude (db) C40 C60 C10 C30 C50 C70 5-7597 (f) 1.0 0.8 0.6 0.4 0.2 0.0 C0.2 C0.4 C1.0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (fs = 1) log magnitude (db) C0.6 C0.8
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 10 4 architectural information (continued) figure 10. a/d or d/a path absolute group delay (hpf disabled) figure 11. a/d or d/a path group delay distortion (hpf disabled) 8 7 6 5 4 3 2 1 0 0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (fs = 1) absolute delay (# of samples) 5-7598 (f) 5-7599 (f) 8 7 6 5 4 3 2 1 0 0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (fs = 1) delay distortion (# of samples)
agere systems inc. 11 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 4 architectural information (continued) figure 12. a/d or d/a path frequency response over f s bandwidth (hpf enabled) figure 13. a/d or d/a path frequency response over 0.5 f s bandwidth (hpf enabled) 5-7600 (f) 10 0 C20 C80 10 C4 10 C3 10 C2 10 C1 10 0 frequency (fs = 1) log magnitude (db) C40 C60 C10 C30 C50 C70 5-7601 (f) 1.0 0.8 0.6 0.4 0.2 0.0 C0.2 C0.4 C1.0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (fs = 1) log magnitude (db) C0.6 C0.8
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 12 4 architectural information (continued) figure 14. a/d or d/a path absolute group delay (hpf enabled) figure 15. a/d or d/a path group delay distortion (hpf enabled) 5-7602 (f) 25 20 15 0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (fs = 1) absolute delay (# of samples) 10 5 5-7603 (f) 8 7 6 5 4 3 2 1 0 0.00.050.100.150.200.250.300.350.400.450.50 frequency (fs = 1) delay distortion (# of samples)
agere systems inc. 13 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 4 architectural information (continued) 4.2.7 digital-to-analog path starting at the bottom right of figure 3 on page 5, the d - s d/a conversion process begins with a 16-bit two's complement pcm signal read from the di serial input. the pcm is interpolated up to 1 mhz in two stages and low-pass filtered at each stage to attenuate 8 khz images. the pcm input is latched into the cdx(d/a) register at a nominal word rate of 8 khz. the signal is then option- ally high-pass filtered. this filter has the same transfer function as the a/d high-pass filter. a digital sample-and-hold increases the word rate by a factor of 5 from 8 khz to 40 khz. the seventh-order iir digital low-pass filter then removes the spectral images between 4 khz and 20 khz and predistorts the pass- band to compensate for the filtering done during the interpolation up to the 1 mhz word rate. the transfer function of this low-pass filter is the same as the one employed in the a/d converter. the output of the low-pass filter feeds a programmable gain adjustment block that serves as a volume control. the gain can be changed in 3 db increments from 0 db to C45 db. the attenuation level is set by writing the ogsel field in the cioc0 register (see table 7 on page 26). the digital modulator block further increases the word rate by a factor of 25 from 40 khz to 1 mhz. through quantization and noise shaping, the digital d - s modula- tor creates 1-bit output words at 1 mhz. the modulator 1-bit output drives a structure combining a 1-bit d/a converter and a second-order switched- capacitor filter having a cutoff frequency of 8 khz (based on a 1 mhz clock). this is all shown as the d/a block in figure 3 on page 5. this is followed by a second-order active chebychev fil- ter having a cutoff frequency of 35 khz. the passband ripple of the analog filters is small enough such that they have virtually no effect on the passband response. the output amplifier buffers the analog filter output. the frequency responses of the a/d and d/a paths are essentially the same. see figures 6 through 15 for the magnitude and delay responses versus frequency. 4.3 programmable features 4.3.1 active/inactive modes the csp1027 has active and inactive modes of opera- tion which are selected by the active field in the cioc0 register (see table 7 on page 26). the default value upon reset and powerup is active = 0 (i.e., inac- tive). in the inactive mode, the codec clocks are dis- abled, data transfers by the codec are disabled, and analog bias currents are shut off. this state is useful in battery-powered applications when prolonged periods of inactivity are expected. it takes approximately 600 ms for the codec to reach full steady-state perfor- mance in going from inactive to active. this is primarily due to the charging of the large external capacitors, c ref and c reg . however, the codec is functionally useful after 100 ms. 4.3.2 input select when the a/d preamplifier is selected (eigs = 0), the insel field of cioc0 (see table 7 on page 26) switches the preamp input between the micin and auxin inputs. when external gain select is used (eigs = 1), the insel field has no effect. 4.3.3 a/d input ranges when the preamplifier is used (eigs = 0), the irsel field of the cioc0 register (see table 7 on page 26) selects the 500 mvp range when irsel = 0 and the 160 mvp range when irsel = 1. irsel has no effect when the external gain select mode is used (eigs = 1). when eigs = 1, the inverting amplifier of figure 5 on page 7 replaces the preamplifier. the input range in this mode is the following: 4.3.4 output mute function the d/a converter output can be selectively muted with the mute field in the cioc0 register (see table 7 on page 26). the default value upon reset is muted (mute = 0). the mute function is implemented (figure 3 on page 5) internally by a mux following the d/a input. placing the mute function here causes the signal at the analog output to gradually decay/rise over approximately 1 ms upon muting/unmuting. this effect is due to the impulse response and group delay of the digital filters. this implementation will reduce any potentially undesirable transient effects, such as pops, when the d/a is muted. v full-scale = rin rfb x 1.578 vp-p
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 14 4 architectural information (continued) 4.3.5 output gains the d/a converter output can be programmed in 3 db increments with the ogsel field in the cioc0 register (see table 7 on page 26) to serve as a volume control. 4.3.6 loopback mode the codec has a programmable loopback mode, repre- sented by the test field in the cioc0 register, (see table 7 on page 26). as shown in figure 3 on page 5, when test = 0, the codec is in its normal mode of operation. when test = 1, the loopback mode is acti- vated. in loopback mode, the 1-bit pdm output signal from the analog modulator is received by the analog demodulator. at the same time, the 1-bit signal output from the digital modulator is received by the sinc-cubic filter in the a/d. this results in the analog input being looped back to the analog output through the a/d and d/a, and the digital input being looped back to the digi- tal output through the digital filters. the loopback mode can be useful for evaluating analog performance of the codec in the target system without going through the digital filters. this mode is also useful for evaluating the response of the digital filters or in evaluating the read/ write functions of the codec and cdx registers without having to provide an analog input to the a/d. 4.3.7 high-pass filter select the high-pass filter in the a/d and d/a can be enabled or disabled with the hpfe field in the cioc3 register (see table 10 on page 29). 4.3.8 dither a dithering scheme is employed in the csp1027 which decorrelates the periodic quantization noise of the d/a modulator to make it white noise. d - s converters are popular due to their high tolerance to component mismatch present in integrated circuit fabrication processes. however, d - s converters may suffer from periodic noise and spurious tone generation (in-band and out-of-band) due to the coarse quantiza- tion and feedback of the d - s modulator. although this periodic noise may exist at very low levels (for example, at about C90 dbm), it may be very objectionable to the listener while having virtually no impact on the resolu- tion of the converter. the csp1027 d/a uses a robust dithering scheme which eliminates any potential prob- lems due to this phenomenon. the dither field in the cioc3 register (see table 10 on page 29) disables this feature. the default value upon reset is dither = 0 (i.e., enabled). when the dither is disabled, the signal-to-noise ratio will gener- ally be about 2 db higher. the dither should be enabled if the csp1027 is used in an audio application, i.e., where this device interfaces to an audio trans- ducer. if the csp1027 is used in an application other than audio, such as data communications, the dither can be disabled if so desired. 4.4 power-on reset 4.4.1 internal the csp1027 has a power-on reset circuit that is ored internally with the inversion of the reset pin, rstb, to form the internal reset (see figure 16 on page 15). the power-on reset circuits inverted output is also an output pin, porb. the porb can be used to provide power-on reset to the system. the power-on reset circuit is composed of two pulse- generating elements, its output being the or of the two. one element is entirely internal and generates a power-on pulse of 1.5 ms to 7.0 ms. the second ele- ment is composed of an input pin, porcap, a resistor connected between porcap and v dd , and an invert- ing input buffer. the user selects the capacitor value to connect between porcap and ground that will gener- ate a power-on pulse of desired width. the pin porcap allows the user to lengthen the power-on reset pulse to a width greater than the internal power- on element provides. the nominal value of the resistor is 155 k w , and the threshold of the inverting input buffer is 0.6 x v dd . the formula that relates the power- on reset pulse delay to the porcap capacitor is as fol- lows: t d = Cr x c x log e (1 C 0.6) t d = 0.9163 x r x c hence, to generate a 14.2 ms power-on reset pulse, one would use a 0.1 f capacitor connected between porcap and v ss . an internal power-on pulse can be initiated after power- on by writing a one to the tstpor field in the cioc3 register (see table 10 on page 29). this causes the internal power-on pulse of 1.5 ms to 7.0 ms to be gen- erated. the pulse resets the device and appears on the porb output pin.
agere systems inc. 15 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 4 architectural information (continued) figure 16. power-on reset diagram figure 17. clock generation 5-7604 (f) power-on pulse generator c porcap v dd r tstpor porb internal reset rstb external component cdifs, cdif0, cdif1, cdif2, cdiv3 ? f1 adjmod, adj ? cdiv1 ? cdiv2 ? cdiv0 ? 125 m u x 1 0 oscillator enable xoscen xlo xhi clk iclk0 iclk cko2 cko1 ck os ck s 5-7560 (f)
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 16 4 architectural information (continued) 4.5 clock generation figure 17 on page 15 shows the clock generation and distribution for the csp1027. the programmable divid- ers can customize the codec sample and master clock rates for a variety of applications in addition to standard 8 khz sampling, while allowing a range of values for the crystal-controlled input clock. in figure 17 on page 15, xoscen is a chip input to enable the crystal oscillator circuit. xlo and xhi are the two leads for the crystal. clk is the chip clock input if the crystal is not used. ck s is the internal codec sample clock, typically 8 khz. ck os is the internal codec oversampled clock, typically 1 mhz. cko1 and cko2 are general-purpose clocks brought out to chip pins. cdiv1 and cdiv2 are pro- grammable dividers with a range from 1 to 31. cdiv0 is programmed to be 1 or 2, but extra clock pulses can be added or subtracted at the output for one period of time following a write to the control register cioc1 . this one- time increase or decrease in the number of clocks is programmed by adjmod and adj and causes a phase shift in the cko1 and ck s output. f1 is an inte- gral or a fractional divider controlled by the five pro- grammable coefficients shown connected to it. with the fractional divide, the period of ck os will vary, but the period of ck s will be constant. the following discussion begins with the crystal oscilla- tor and is followed by a detailed description of each divisor block. section 7.5 on page 45 provides some examples of how to program the clocks. 4.5.1 crystal oscillator the csp1027 has a selectable on-chip clock oscillator. a logic 1 on the xoscen pin enables the crystal oscil- lator. a logic 0 disables the oscillator, powers it down, and selects the input buffer connected to the clk pin. to use the oscillator, select a 20 mhz to 30 mhz funda- mental-mode crystal with a series resistance less than 60 w and a mutual capacitance less than 7.0 pf. con- nect the crystal between the xlo and xhi pins, and add 10 pf capacitors between xlo and ground, and xhi and ground. the xoscen pin enables and dis- ables the crystal oscillator. see the application informa- tion on optimizing the oscillator performance. 4.5.2 clock divider 2 figure 18. clock divider 2 the cdiv2 field in cioc0 (see table 7 on page 26) sets the clock divider that generates the output clock, cko2. the clock output is a general-purpose clock that can be used to clock external logic or processors. cdiv2 ranges from 1 to 31, with 0 holding the output low. rstb going low sets cdiv2 to 16. cko2 is active while rstb is low and synchronized by rstb going high. 4.5.3 clock divider 0 figure 19. clock divider 0 the cdiv0 field in cioc1 (see table 8 on page 27) sets the clock divider that generates the internal clock 0 (iclk0) to either divide by one or divide by two. the adjmod and adj fields in cioc1 are used to adjust the phase of iclk0 by increasing or decreasing the rate of iclk0 for a burst of pulses, one time only. this event occurs each time control register cioc1 is written with nonzero values of adj. for example, let cdiv0 be set to 2, adj to seven, and adjmod to one (advance). after this word is written to the cioc1 regis- ter, seven iclk0 pulses will occur at the same rate as iclk, not divided by two. these seven clock pulses shift the phase of ck os , ck s , and cko1 earlier, thus advancing these clocks. if adjmod is set to zero (retard), the 2 becomes a 3 for seven pulses of iclk0. the cdiv0 clock divider is temporarily changed internally so that it divides by one greater, to retard the clocks, or one less, to advance the clocks, for the spec- ified number of iclk0 cycles. note that the cdiv0 clock divider must be set to divide by two in order to advance and retard the clocks. if cdiv0 clock divider is set to divide by 1, one can only retard the clocks. ? cdiv2 iclk cko2 5-7589 (f) ? cdiv0 iclk iclk0 adjmod, adj 5-7588 (f)
agere systems inc. 17 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 4 architectural information (continued) cdiv0 has values of 1 or 2, adjmod is 0 or 1, and adjmod ranges from 1 to 127, with 0 selecting no clock adjust. rstb going low sets cdiv0 to 2. iclk0 is active while rstb is low and synchronized by rstb going high. 4.5.4 clock divider 1 figure 20. clock divider 1 the cdiv1 field in cioc1 (see table 8 on page 27) sets a clock divider that generates the cko1 output clock. this general-purpose clock output can be used for clocking another codec in the system, such as the csp1084. the ability to phase adjust the output clock and the codec sampling clock simultaneously is an important feature. cdiv1 ranges from 1 to 31, with 0 disabling the output. rstb going low sets cdiv1 to 16. cko1 is active while rstb is low and synchro- nized by rstb going high. 4.5.5 sampling clocks generation figure 21. sampling clocks generation the oversampling codec clock ck os , typically 1 mhz, is used in the front sections of the a/d and the back sections of the d/a. the lower-frequency codec clock, ck s , typically 8 khz, is the sample clock at the output of the a/d and the input to the d/a. the sampling clock frequency, f s , is the oversampling clock frequency, f os , divided by 125 (the fixed oversampling ratio). the divide by 125 must remain fixed, since it is constrained by the architecture of the codec digital filters. many sys- tems, however, have fixed high-frequency clocks and fixed sampling clocks, so it is necessary to have a great deal of flexibility in the creation of the codec clock ck s . the csp1027 solves this problem in a unique way, by providing a programmable, fractional divider, f1. f1 is the programmable ratio between iclk0 and ck os . the equation for f1 is: where 3 m 64, 0 n 62, and s = {1, C1}; or m = 2, 0 n 62, and s = 1; or m = 1, n = 0, and s = 1. m is encoded by cdiv3 (see table 3 on page 18), n is encoded by cdif0, cdif1, and cdif2 (see table 5 on page 19), and s is encoded by cdifs (see table 4 on page 18). ck s is generated by dividing ck os by 125. the fre- quency of ck s can be described by: note that when n = 0, iclk0 is simply divided by the integer m to create the oversampling clock, ck os . this is the preferred method for generating the sampling clock. if n 1 0, the fractional division results in an over- sampling clock, ck os , whose period varies with time such that the average period is the desired fraction. this variation in the oversampling clock period is mini- mized by the clock generator but can cause distortion in the codec. because the denominator of the fraction is fixed at 125, the period of the sampling clock, ck s, will be an integer multiple of the period of the internal clock, iclk0, and will not vary. this is more clearly shown by the following equation: the expanded equation below explains what is hap- pening in the time domain: during each sampling period, , there are (125 C n) oversampling clock cycles of period and n oversampling clock cycles of period . the n oversampling clock cycles are evenly distributed among the (125 C n) oversampling clock cycles to min- imize the distortion due to oversampling clock cycles of differing period. the values for cdif[02] in table 5 on page 19 have been selected to achieve the even dis- tribution. ? cdiv1 iclk0 cko1 5-7587 (f) ? f1 iclk0 ck s ? 125 ck os cdifs, cdif0, dsif1, cdif2, cdiv3 5-7586 (f) f1 m s n 125 --------- - ? ?? + = f s f os 125 ? f iclk 0 ms n 125 --------- - + ? ?? ? 125 ? == f iclk 0 f s ---------------- 125 m () sn () + = 1 f s ---- - 125 n C () m f iclk 0 ---------------- n ms + () f iclk 0 ------------------- - + = 1 f s ---- - m f iclk 0 ---------------- ms + () f iclk 0 ------------------- -
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 18 4 architectural information (continued) the procedure for selecting m, s, and n is illustrated in section 7.5 on page 45. the ranges for the programmable dividers are summarized in table 2. table 2. programmable divider summary clock ratio iclk/iclk0 iclk0/ck os iclk0/ck s iclk/cko2 iclk0/cko1 variable name cdiv0 125m n cdiv2 cdiv1 range of values 1, 2 1, 2 to 64.496 125, 250 to 8062 off, 1 to 31 off, 1 to 31 encoding 0, 1 see tables 3 through 5. see tables 3 through 5. 0 to 31 0 to 31 table 3. cdiv3 value for each m m cdiv3 1 00 0001 2 00 0010 . . . . . . 62 11 1110 63 11 1111 64 00 0000 table 4. cdifs value for each s s cdifs +1 0 C1 1 m n 125 --------- -
agere systems inc. 19 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 4 architectural information (continued) table 5. cdif0, cdif1, cdif2 values for each n n cdif0 cdif1 cdif2 n cdif0 cdif1 cdif2 0 00 0000 00 0000 0 0000 32 00 0100 10 1000 0 0010 1 11 1111 00 0000 0 0000 33 00 0100 10 0100 0 0010 2 11 1101 00 0010 0 0000 34 00 0011 00 0010 1 0010 3 10 1001 00 0010 0 0000 35 00 0011 00 0010 1 0100 4 01 1111 00 0000 0 0000 36 00 0011 00 0010 0 0100 5 01 1001 00 0000 0 0000 37 00 0011 00 0011 1 0010 6 01 0101 10 0110 0 0000 38 00 0011 00 0011 0 0010 7 01 0010 10 0100 0 0000 39 00 0011 00 0100 0 0010 8 00 1111 00 0010 0 0000 40 00 0011 00 0111 0 0000 9 00 1110 10 0101 0 0000 41 00 0011 00 1110 0 0000 10 00 1100 00 0010 0 0000 42 00 0011 11 0110 0 0000 11 00 1011 00 0010 0 0010 43 00 0011 10 1001 0 0000 12 00 1010 00 0010 0 0010 44 00 0011 10 0110 0 0000 13 00 1001 00 0010 1 0010 45 00 0011 10 0100 0 0010 14 00 1001 10 0111 0 0010 46 00 0011 10 0011 0 0010 15 00 1000 00 0011 0 0000 47 00 0010 00 0010 1 0010 16 00 1000 10 0100 0 0010 48 00 0010 00 0010 1 0011 17 00 0111 00 0011 0 0000 49 00 0010 00 0010 1 0101 18 00 0111 10 1001 0 0010 50 00 0010 00 0010 0 0000 19 00 0110 00 0010 1 0011 51 00 0010 00 0010 0 0011 20 00 0110 00 0011 0 0010 52 00 0010 00 0010 0 0010 21 00 0110 10 1011 0 0000 53 00 0010 00 0011 1 0011 22 00 0101 00 0010 1 0010 54 00 0010 00 0011 0 0011 23 00 0101 00 0010 0 0010 55 00 0010 00 0011 0 0010 24 00 0101 00 0100 0 0010 56 00 0010 00 0100 0 0010 25 00 0101 00 0000 0 0000 57 00 0010 00 0101 0 0000 26 00 0101 10 0100 0 0010 58 00 0010 00 0110 0 0000 27 00 0100 00 0010 1 0011 59 00 0010 00 0111 0 0010 28 00 0100 00 0010 0 0011 60 00 0010 00 1010 0 0010 29 00 0100 00 0011 0 0000 61 00 0010 00 1111 0 0010 30 00 0100 00 0101 0 0010 62 00 0010 00 0000 0 0000 31 00 0100 00 0000 0 0000
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 20 4 architectural information (continued) 4.6 serial i/o configurations 4.6.1 codec data transfer when the codec is active, active = 1 (see table 7 on page 26), it loads data into the cdx(a/d) and empties data from the cdx(d/a) register (see figure 3 on page 5) at the sampling frequency, f s (which is 8 khz based on a 1 mhz oversampling frequency). the codec data transfers occur independent of the serial input/output data transfers described below. the data is double buffered, allowing the codec to transfer data to or from the cdx while the serial i/o is shifting data into or out of the shift registers ( isr and osr ). when the codec is set to inactive, active = 0, there are no codec data trans- fers to the cdx(a/d) or from the cdx(d/a) . the internal status flag is set high when cdx(a/d) is loaded and cdx(d/a) is emptied. loading data from the cdx(a/d) into the output shift register ( osr ) or loading data from the input shift register ( isr ) into the cdx(d/a) due to a serial i/o transaction, clears the internal sta- tus flag. the internal status flag can be observed on the data output (do) pin in the passive mode and causes data transfers in the active and multiprocessor modes. 4.6.2 codec control writes the four control registers are written through the serial port. the serial address (sadd) selects between con- trol and data transfers. bits 15 and 14 of the control word being transferred select which control register, cioc0 , cioc1 , cioc2 , or cioc3 , is written (i.e., cioc0 : bit[15:14] = 00, cioc1 : bit[15:14] = 01, etc.). 4.6.3 serial i/o port overview the csp1027 serial i/o unit is an asynchronous, full- duplex, double-buffered channel operating at up to 20 mbits/s that easily interfaces with other agere fixed- point dsps (i.e., dsp16a and dsp1610/1616/1617/ 1618) in a single or multiple dsp environment. com- mercially available codecs and time-division multi- plexed (tdm) channels can be interfaced to the csp1027 device with little, if any, external logic. the serial interface is a subset of the standard agere dsp serial i/o and is comprised of eight pins: n a single passive serial input/output clock (iock). n a combined input load, output load, and synchroni- zation (sync). n serial data input (di). n serial data output (do). n serial address (sadd). n three serial mode select pins (smode[2:0]). the csp1027's serial i/o is different from the standard agere serial i/o in a number of ways: n the smode[1:0] pins configure the serial i/o port into one of four possible ways: a passive sio config- uration, an active sio configuration, and two multi- processor sio configurations. n a fixed most significant bit (msb) first data format. n a fixed 16-bit data mode. n the serial address (sadd) is an input during the passive and active sio configurations to select between data and control sio transfers. it is intended to be connected to the dsps sadd pin, which is an output during passive and active sio. note that the dsp's sadd output is inverted and is composed of two 8-bit fields that are shifted out least significant bit (lsb) first. n the multiprocessor mode time slots and serial addresses are restricted to two sets, one of which is selected based on the state of smode0. n the smode2 pin should always be tied low for the serial i/o port to operate as described. n the frequency of the serial i/o interface clock input iock (f iock ) must be greater than the frequency of the internal oversampling clock (f iock ).
agere systems inc. 21 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 4 architectural information (continued) figure 22. passive communication and connections 4.6.4 passive i/o configuration (smode[1:0] = 00) the passive sio configuration allows the user maxi- mum flexibility in interfacing the csp1027 to a variety of system hardware configurations. it requires that the user supply a serial input/output clock (iock) and per- form data transfers at the sampling rate, f s . serial data transfers can be made to occur at the sampling rate by applying a clock that is synchronous with the codec clock, iclk, to the sync pin or by polling the codec status flag, which indicates that the cdx(a/d) register is full and the cdx(d/a) register is empty. the status flag appears on do when the sadd pin selects a con- trol word. passive sio is selected by setting both smode1 and smode0 low. the input/output clock (iock) is an input and the common input/output load, sync, (equivalent to a dsp16a's ild and old tied together) is also an input. serial data input (di) is an input and serial data output, do, is an output. the serial address (sadd) is an input, which determines if the transfer is to the con- trol registers, cioc [0:3], or the data register, cdx(d/a) . a high-to-low transition of sync pin signal, latched by the next rising edge of iock, initiates the start of an input and output transaction. if the csp1027's output buffer, cdx(a/d) , is full, it will be loaded into the output shift register ( osr ) and shifted out on the do pin. the csp1027 shifts in the data from the di pin into its input shift register ( isr ). a serial transmit address on the sadd line is received simultaneously with data on the di line. if sadd is high for the first 15 bits, correspond- ing to a zero serial transmit address, this causes the isr to be latched into cdx(d/a) after 16 bits have been shifted in. if sadd is low for any of the first 15 bits, cor- responding to a nonzero transmit address, this causes the isr to be latched into cioc [0:3] and also changes the output data stream on do to display the internal codec status flag. if sadd is low for any clock cycle, while not involved in a serial transaction, the codec status flag is displayed on the do pin until the next data transfer. an example of the passive sio configuration is shown in figure 22. the dsp supplies both the serial clock (iock) and the sampling synchronization signal to sync, or polls the internal codec status flag to deter- mine when a data transmission is needed. this config- uration allows the user maximum flexibility in interfacing the csp1027 to a variety of other system hardware configurations. a/d data clock control/data address input/output load do ick ild old di ock do iock sadd sync di dsp csp1027 smode0 smode1 smode2 d/a data sadd 5-7590 (f)
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 22 4 architectural information (continued) figure 23. active communication and connections 4.6.5 active i/o configuration (smode[1:0] = 01) the active sio configuration causes the csp1027 to generate an active input/output load (sync) to perform input/output transmissions when needed. the user supplies only a serial input/output clock (iock). the active sio is selected by setting smode1 low and smode0 high. the input/output clock (iock) is an input and the input/output load (sync) is an output. while the codec is inactive, active = 0 (see table 7 on page 26), sync generates serial i/o transfers at an iock 16 rate to allow loading the codec control regis- ters, cioc [0:3]. while the codec is active, active = 1 (see table 7 on page 26), sync generates serial i/o transfers at the sampling rate, synchronized to the codec's emptying of the cdx(d/a) and loading of the cdx(a/d) . the serial address (sadd) functions as described previously for the passive sio configuration, but with the sync pin being active and determining data transfers, the need for polling the codec status flag is eliminated. the serial address during the data stream still is used to determine whether data in the input shift register is latched into cdx(d/a) or cioc [0:3] at the end of the transaction. note that cioc0 , with active = 1, should be written last since this will change the rate of serial i/o transfers from iock 16 to the sampling rate. an example of the active sio configuration is shown in figure 23. the dsp supplies the serial clock (iock) while the csp1027 supplies the input/output load, sync. the serial address (sadd) is connected so that writing the dsp's srta register addresses the cdx(d/a) when srta = 0x0, or the cioc0 , cioc1 , cioc2 , cioc3 when srta = 0x1. the dsp can activate the codec by writing the cioc0 register in the csp1027, and then let- ting its input buffer full flag (ibf) indicate when the csp1027 has transferred data. this is the preferred interface for a single dsp and a csp1027. a/d data clock control/data address input/output load do ick ild old di ock do iock sadd sync di dsp csp1027 smode0 smode1 smode2 d/a data v dd sadd 5-7591 (f)
agere systems inc. 23 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 4 architectural information (continued) figure 24. multiprocessor communication and connections 4.6.6 multiprocessor configuration (smode[1:0] = 1x) the csp1027 serial i/o supports a multiprocessor mode that allows multiple devices to be connected together to provide data transmission between any of the individual devices. this mode requires no external hardware and uses a time-division multiplex (tdm) interface with eight time slots per frame. figure 24 shows an example of a multiprocessor system with multiple dsps and a csp1027. the following pins are connected together to form a four-wire bus: n di and do from the csp1027s and dsps form a data line referred to as data. n iock from the csp1027s and ick and ock from the dsps form a clock line referred to as ck. n sadd from the csp1027s and dsps form an address line referred to as add. n sync from the csp1027s and dsps form a synchro- nization line referred to as syn. figure 25 on page 25 shows the time-slot allocation tim- ing used in multiprocessor mode. one frame is defined as the time between syn high-to-low transitions. each frame is divided into eight time slots of 16 bits each. a high-to-low transition of syn defines the beginning of time slot 0 and also resynchronizes any devices which are operating on the multiprocessor bus with syn as an input. note that the dsp device which drives the multi- processor bus during time slot 0 also drives the syn line. each csp1027 sends data in a time slot determined by its smode0 pin. each dsp sends data in a time slot or time slots determined by its tdms register. only one device can be assigned a particular time slot, and each of the eight time slots must be assigned to a device (note that one device can be assigned more than one time slot). these requirements must be met by the user's choice of csp1027s smode0 connections and the dsps tdms register contents. a csp1027 is assigned to time slot 2 if smode0 is low or to time slot 5 if smode0 is high. this allows up to two csp1027s to be placed on a multiprocessor bus. the dsp input/output format can be configured to either most significant bit (msb) first or least significant bit (lsb) first. the csp1027 only supports msb first format; hence, the dsps connected on a multiprocessor bus must be using msb first data format, configured in the sioc register, when transferring and receiving data and control words with the csp1027. 5-4181 (f). c dev7 data ck add syn do ick sadd sync di ock dev1 do ick sadd sync di ock v dd dev0 do iock sadd sync di (dsp1616) (dsp1610) (csp1027) smode1 smode0 smode2
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 24 4 architectural information (continued) during each time slot (see figure 26 on page 25), the device that is assigned to that time slot drives the add and data lines. if the assigned device's output buffer is full, it loads its output shift register and shifts the 16 bits of data, msb first, out do onto the data line. the 8-bit transmit address is inverted and shifted out, lsb first, onto the add line at the same time as the first 8 bits of data. the inverted 8-bit protocol information is then shifted out, lsb first, on the add line at the same time as the last 8 bits of data. the csp1027s transmit address, at[7:0], is determined by the smode0 pin (see table 6 on page 25). the dsps transmit address is determined by the srta register. the csp1027s pro- tocol information is always all zeros, which is inverted to appear as all ones on the add line. the dsps pro- tocol information is determined by the saddx register. if during a time slot the assigned device's output buffer is empty, then zeros are shifted out on the data line and zeros are shifted and inverted to become ones on the add line. during each time slot, each device receives the data on the data line and inverts and receives the address and protocol information on the add line. each device com- pares the transmitted 8-bit address with its receive address. if the transmitted address and the device's receive address have at least one occurrence of a one in the same bit location, the address matches and the device transfers the data from the input shift register to its input buffer. if the transmitted address and the receive address do not match, the data remains in the input shift register and is overwritten during the next time slot. the dsp's receive address is determined by its srta register. each csp1027 has two receive addresses, one for data and another for control, the values of these two addresses are determined by the smode0 pin (see table 7 on page 26). when the data receive address matches, the input shift register is loaded into the cdx(d/a) register. when the control receive address matches, the input shift register is loaded into one of the four cioc registers, based upon the two most significant bits of the 16-bit word. the csp1027 ignores the protocol information. multiprocessor communication with a csp1027 is intended to follow the sequence: n the dsp writes the control registers, cioc [0:3], in the csp1027 to configure the clock dividers and codec. the codec is also activated. n the csp1027s a/d fills the output buffer, cdx(a/d) , and empties the input buffer, cdx(d/a) , at the same time. this causes the a/d data to be transmitted by the csp1027 to the dsp during the next csp1027 time slot. the dsps receive address is set to match the csp1027s transmit address. n when the dsp receives a/d data from the csp1027, it responds by sending d/a data to the csp1027 dur- ing the dsps next time slot. the dsps transmit address is set to match the csp1027s data receive address. the new data is loaded into the csp1027s cdx(d/a) register to be used as the next d/a sample. n if the dsp wants to send a control word to the csp1027 to change the configuration or inactivate the codec, this can be done by setting the dsp's transmit address to match the codec's control receive address. note that since the csp1027 sends all zeros for the protocol information, this will have to be used to identify the a/d data from the csp1027. if two csp1027s are connected to the multiprocessor bus and the dsp's receive address is set to match both csp1027's trans- mit addresses, the dsp will have to identify which a/d data came from which csp1027 by the order in which the data arrives, since both csp1027s will be sending the same protocol information.
agere systems inc. 25 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 4 architectural information (continued) figure 25. multiprocessor frame timing figure 26. multiprocessor time-slot timing table 6. hardwired csp1027 multiprocessor time slot and addresses smode0 = 0 smode0 = 1 transmit time slot 2 5 data, cdx(a/d) , transmit address [7:0] 0000 0100 0010 0000 data, cdx(d/a) , receive address [7:0] 0000 1000 0100 0000 control, cioc [0:3], receive address [7:0] 0001 0000 1000 0000 5-4185 (f).a time slot 01 2 3 456 7 0 ck syn data add d[15:0] d[15:0] d[15:0] d[15:0] d[15:0] d[15:0] d[15:0] d[15:0] d[15:0] a[15:0] a[15:0] a[15:0] a[15:0] a[15:0] a[15:0] a[15:0] a[15:0] a[15:0] d0 ck syn data add d15 d14 d15 d14 ad0 ad7 as0 as7 ad0 5-7605 (f)
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 26 5 register information tables 7 through 10 describe the programmable registers of the csp1027 device. 5.1 codec i/o control 0 (cioc0) register table 7. codec i/o control 0 (cioc0) register bit 1514 13 12 118 7 6 5 40 field reg test active ogsel mute irsel insel cdiv2 field value description reg 00 indicates control register 0. test 0* 1 * value upon reset. normal operation. testability modeanalog and digital loopback. active 0* codec set to inactive mode (i.e., powerdown). 1 codec set to active mode. ogsel 1111 output gain adjustment of 0 db. 1110 output gain adjustment of C3 db. 1101 output gain adjustment of C6 db. . . . . . . 0001 output gain adjustment of C42 db. 0000* output gain adjustment of C45 db. mute 0* output signal muted. 1 output signal not muted. irsel 0* microphone preamplifier input range: 500 mvp. 1 microphone preamplifier input range: 160 mvp. insel 0* select microphone input, micin. 1 select auxiliary input, auxin. cdiv2 0 0000 output clock 2, cko2, disabled. 0 0001 output clock 2, cko2 = iclk 1. 0 0010 output clock 2, cko2 = iclk 2. . . . . . . 1 0000* output clock 2, cko2 = iclk 16. . . . . . . 1 1110 output clock 2, cko2 = iclk 30. 1 1111 output clock 2, cko2 = iclk 31.
agere systems inc. 27 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 5 register information (continued) 5.2 codec i/o control 1 (cioc1) register table 8. codec i/o control 1 (cioc1) register bit 1514 13 126 5 40 field reg adjmod adj[6:0] cdiv0 cdiv1 field value description reg 01 indicates control register 0. adjmod 0* * value upon reset. select retard mode for internal clock, iclk0, adjustment. 1 select advance mode for internal clock, iclk0, adjustment. adj 000 0000* internal clock, iclk0, not adjusted. 000 0001 internal clock, iclk0, adjusted by one iclk cycle for one iclk0 cycle. 000 0010 internal clock, iclk0, adjusted by one iclk cycle for two iclk0 cycles. . . . . . . 111 1110 internal clock, iclk0, adjusted by one iclk cycle for 126 iclk0 cycles. 111 1111 internal clock, iclk0, adjusted by one iclk cycle for 127 iclk0 cycles. cdiv0 0 internal clock, iclk0 = iclk 1. 1* internal clock, iclk0 = iclk 2. cdiv1 0 0000 output clock 1, cko1, disabled. 0 0001 output clock 1, cko1 = iclk0 1. 0 0010 output clock 1, cko1 = iclk0 2. . . . . . . 1 0000* output clock 1, cko1 = iclk0 16. . . . . . . 1 1110 output clock 1, cko1 = iclk0 30. 1 1111 output clock 1, cko1 = iclk0 31.
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 28 5 register information (continued) 5.3 codec i/o control 2 (cioc2) register table 9. codec i/o control 2 (cioc2) register bit 1514 13 12 116 50 field reg reserved cdifs cdif0 cdiv3 field value description reg 10 indicates control register 0. reserved 0* * value upon reset. reserved, always write 0. cdifs 0* sampling rate, ck s = iclk0 (cdiv3 x 125). sampling rate, ck s = iclk0 256. ( note: cdiv3 must be set to 2.) 1 sampling rate, ck s = iclk0 1458. ( note: cdiv3 must be set to 12.) w sampling rate, ck s = iclk0 (125 x m + s x n). see section 4.5 on page 16. cdif0 00 0000* sampling rate, ck s = iclk0 (cdiv3 x 125). 01 0101 sampling rate, ck s = iclk0 256. ( note: cdiv3 must be set to 2.) 00 0011 sampling rate, ck s = iclk0 1458. ( note: cdiv3 must be set to 12.) ww wwww sampling rate, ck s = iclk0 (125 x m + s x n). see section 4.5 on page 16. cdiv3 00 0001 oversampling clock, ck os = iclk0 1. 00 0010 oversampling clock, ck os = iclk0 2. . . . . . . 11 1111 oversampling clock, ck os = iclk0 63. 00 0000* oversampling clock, ck os = iclk0 64. ww wwww sampling rate, ck s = iclk0 (125 x m + s x n). see section 4.5 on page 16.
agere systems inc. 29 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 5 register information (continued) 5.4 codec i/o control 3 (cioc3) register table 10. codec i/o control 3 (cioc3) register bit 1514 13 12 11 106 50 field reg tstpor hpfe dither cdif2 cdif1 field value description reg 11 indicates control register 0. tstpor 0* 1 * value upon reset. normal operation. test on-chip power-on reset pulse generator. hpfe 0* enable high-pass filter in a/d and d/a. 1 disable high-pass filter in a/d and d/a. dither 0* enable dither on d/a converter. 1 disable dither on d/a converter. cdif2 0 0000* sampling rate, ck s = iclk0 (cdiv3 x 125). 0 0000 sampling rate, ck s = iclk0 256. ( note: cdiv3 must be set to 2.) 0 0000 sampling rate, ck s = iclk0 1458. ( note: cdiv3 must be set to 12.) w wwww sampling rate, ck s = iclk0 (125 x m + s x n). see section 4.5 on page 16. cdif1 00 0000* sampling rate, ck s = iclk0 (cdiv3 x 125). 10 0110 sampling rate, ck s = iclk0 256. ( note: cdiv3 must be set to 2.) 11 0110 sampling rate, ck s = iclk0 1458. ( note: cdiv3 must be set to 12.) ww wwww sampling rate, ck s = iclk0 (125 x m + s x n). see section 4.5 on page 16.
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 30 6 signal descriptions figure 27. csp1027 pinout by interface figure 27 shows the pinout by interface for the csp1027. the signals can be separated into five inter- faces as shown. these interfaces and the signals that comprise them are described below. 6.1 clock interface the clock interface consists of the clock input, crystal oscillator, and clock outputs for the codec. 6.1.1 clk clock input: the input clock for the csp1027 when the xoscen is a logic low. codec operation restricts clk to integer frequencies from 1 mhz to 40 mhz or specific multiples of 8 khz. when xoscen is tied to logic high, the clk input is not selected but should be tied low or high to minimize input buffer power. 6.1.2 xlo crystal input: the crystal for csp1027 voice band codec is connected between xlo and xhi. when the crystal is not being used, this pin is to be left floating and the cmos clock applied to clk. 6.1.3 xhi crystal output: the crystal for csp1027 handset codec is connected between xlo and xhi. when the crystal is not being used, this pin is to be left floating and the cmos clock applied to clk. 6.1.4 xoscen crystal oscillator enable: when a logic high, the crystal oscillator is selected for xlo and xhi pins. when a logic low, the input buffer is selected for clk pin and the crystal oscillator is powered down. note: the xoscen pin does not have a pull-up or pull-down device. make sure that it is tied to v dd , tied to v ss , or driven by valid logic levels. csp1027 clk xoscen xlo xhi cko1 cko2 rstb porcap porb iock sync di do sadd smode0 smode1 smode2 eigs micin auxin v reg aoutp aoutn refc clock interface reset interface serial interface external gain select interface analog interface 5-7606 (f)
agere systems inc. 31 data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 6 signal descriptions (continued) 6.1.5 cko1 clock out 1: iclk cdiv1 (see table 8 on page 27). general-purpose output clock that can be used by a baseband codec, such as the csp1084. 6.1.6 cko2 clock out 2: clk cdiv2 (see table 7 on page 26). general-purpose output clock that can be used by a processor, such as the dsp1616. 6.2 reset interface the reset interface consists of the reset input, power- on reset input, and power-on reset output for the codec. 6.2.1 rstb reset: a high-to-low transition causes entry into the reset state. the cioc [0:3] register bits are set to their default states. 6.2.2 porb power-on reset: a high-to-low transition indicates entry into the power-on reset state. 6.2.3 porcap power-on reset capacitor: a capacitor is to be attached to this pin for the power-on reset circuit. por- cap has an internal resistor (nominal value of 155 k w ) connected to digital power, v dd . 6.3 serial i/o interface the serial i/o interface consists of the serial clock input, synchronizing signal, data input, data output, serial address, and serial modes for the codec. 6.3.1 smode 0 serial mode 0: configures the csp1027 serial i/o interface. when in active/passive mode (smode1 low), sync is an output when smode0 is high, and sync is an input when smode0 is low. in multiprocessor mode (smode1 high), smode0 selects between two possible time slots, and between two possible transmit and receive address combinations. see table 6 on page 25 in the architectural information for the addresses. 6.3.2 smode1 serial mode 1: configures the csp1027 serial i/o interface to multiprocessor mode when active-high; oth- erwise, active/passive mode is selected when low. 6.3.3 smode2 serial mode 2: must be tied low to configure the csp1027 serial i/o interface as described. 6.3.4 di serial data input: serial data input is latched on rising edge of iock, msb first. di and do should be con- nected together when in multiprocessor mode. 6.3.5 do serial data output: serial data output from the output shift register ( osr ), msb first, when the data register, cdx(a/d) , is selected or codec status flag when the control registers, cioc [0:3], are selected. when an out- put, do changes on the rising edges of iock. di and do should be connected together when in multiproces- sor mode, smode1 high. 6.3.6 iock serial input/output clock: input clock for serial pcm input and output data. note: the frequency of the serial i/o interface clock input iock (f iock ) must be greater than the fre- quency of the internal oversampling clock ck os (f ckos ). 6.3.7 sync serial input/output load strobe and sync: when not in multiprocessor mode, the falling edge of sync indicates the beginning of a serial input and a serial output word. the falling edge of sync loads the output shift register ( osr ) from the codec data register ( cdx(a/d) ). sixteen iock clock cycles after the falling edge of sync, the codec data ( cdx(d/a) ) or control register ( cioc ) is loaded from the input shift register ( isr ). sync is an input when the smode0 pin is low and an output when the smode0 pin is high. in multiprocessor mode, sync is the multiprocessor synchronization input signal. a falling edge of sync indicates the first word of a tdm i/o stream and causes the resynchronization of the internal input and output load generators.
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 32 6 signal descriptions (continued) 6.3.8 sadd serial address: when not in multiprocessor mode, sadd is an input that selects between the codec data registers, cdx(d/a) and cdx(a/d) , and codec control registers, cioc [0:3]. sadd is inverted and latched on the rising edge of iock and compared against a zero for data and a one for control, to determine if input data on di is loaded from the input shift register ( isr ) into cdx(d/a) or one of cioc [0:3]. once sadd indicates a control word, the internal codec status flag appears on do, replacing cdx(a/d) . while not performing a serial transmission, sadd low causes the internal codec sta- tus flag to be output on do. in multiprocessor mode, sadd is an output when the tdms time slot dictates a serial output transmission; oth- erwise, it is an input. while an output, sadd is the inverted 8-bit serial transmit address output, lsb first. sadd changes on the rising edges of iock. while an input, sadd is inverted and latched on the rising edge of iock and compared against the cdx(d/a) and cioc [0:3] serial receive addresses to determine if input data on di is loaded from the input shift register ( isr ) into cdx(d/a) or cioc . 6.4 external gain control interface the external gain control interface consists of one input. 6.4.1 eigs external input gain select: a logic low or no connect selects the microphone preamplifier. a logic high selects the single op amp input mode where external resistors set the a/d input range. note that eigs is a digital pin whose input levels are relative to digital power and ground (v dd and v ss ). 6.5 digital power and ground v dd digital power supply: 3.0 v to 5.0 v supply. v ss digital ground: 0 v. 6.6 analog interface the analog interface consists of the two inputs, two out- puts, a regulated output voltage reference, and a capac- itor connection for the codec. 6.6.1 micin analog input from microphone: low-level analog sig- nal from electret condenser microphone selected by insel bit in codec control register, cioc0 (see table 7 on page 26). 6.6.2 auxin analog input from auxiliary: when used in preampli- fier mode (eigs = 0), auxin is a low-level analog signal selected by insel bit in codec control register, cioc0 (see table 7 on page 26). the characteristics of auxin are identical to micin. when used in external gain select mode (eigs = 1), auxin is the output of the inverting amplifier. the insel bit has no effect in this mode. 6.6.3 aoutp noninverting analog output: in conjunction with aoutn, this output can drive a 2 k w load in differential mode or a 1 k w load ac-coupled to analog ground. 6.6.4 aoutn inverting analog output: in conjunction with aoutp, this output can drive a 2 k w load in differential mode or a 1 k w load ac-coupled to ground. 6.6.5 v reg regulated output voltage: for electret condenser microphone. vout = 3 v 10%, iout = 250 a max. a 1 f and 0.1 f ceramic type x7r capacitor to ground must be provided at this pin (see figure 28 on page 34). 6.6.6 refc external capacitor connection: internal voltage regu- lator bypassing. a 0.22 f ceramic type x7r capacitor to ground must be provided at this pin. 6.7 analog power and ground v dda analog power supply: 5.0 v supply. v ssa analog ground: 0 v.
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 33 7 application information this section begins with application information for the analog section, followed by power distribution, crystal oscillator, and codec clock generation programming examples. 7.1 analog information the a/d input block is covered first, followed by the d/a, and the microphone voltage regulator. 7.1.1 a/d in the preamplifier mode figure 28 on page 34 shows a typical telephone hand- set application. the codec is shown with the preamp mode (eigs = v ss ) selected and connected to a micro- phone. the analog-to-digital conversion path begins with an on-chip preamplifier front end having two single-ended inputs. the preamp inputs are micin and auxin. selection of micin or auxin is made via the insel field in the cioc0 register (see table 8 on page 27) and can be dynamically changed, as desired. the electrical specifications for both inputs are the same. an off-chip ac-coupling capacitor, cin, is required before each input. however, if either input is unused, it may be left unconnected (floating). the input resis- tance (rin) to either micin or auxin is approximately 40 k w . the recommended value of cin is 0.15 f. this creates a high-pass filter pole at approximately 26 hz. a larger capacitor value may be used if desired, in order to allow lower frequencies to pass to the a/d con- verter, but smaller capacitor values are not recom- mended. 7.1.2 a/d in the external input gain select mode the external input gain select (eigs = v dd ) is used when the input range is set by the user (see section 4.3 on page 13). the a/d input circuitry of figure 28 on page 34 is modified as shown in figure 5 on page 7. when eigs = v dd , the following notes apply. 1. the recommended range of values for the feedback resistor and capacitor are the following: 10 k w rfb 45 k w and 150 pf cfb 680 pf. 2. the external resistor ratio accuracy directly impacts the absolute accuracy of the a/d path. a 1% ratio error adds 86 mdb of absolute gain error. 3. the a/d input sampling switches have an effective bandwidth on the order of 15 mhz. the amplifier unity gain frequency is on the order of 3 mhz. high- frequency noise in the 1 mhz to 50 mhz range that couples to the auxin pin will be somewhat attenu- ated by the amplifier output impedance, but a signifi- cant portion will be sampled by the a/d and aliased down to the baseband. special care in circuit board layout is required to keep noise sources from cou- pling into the auxin or micin pins so that the noise and distortion performance shown in table 16 on page 52 can be achieved. the codec is not as sensitive to wideband noise when the preamplifier is used (eigs = v ss ) because the a/d inputs are driven from an on-chip low-pass filter. 4. the external gain mode input circuitry of figure 5 on page 7 is an integrator with a great deal of loss. the frequency response of table 16 on page 52 assumes that the rfb cfb corner frequency is 25 khz so the 3 khz droop is less than 65 dbm. sim- ilarly, the cin rin corner frequency is set to 7 hz. these rc combinations create a bandpass anti- aliasing filter with corner frequencies given by: when selecting component values, verify that the a/d frequency response will still meet the application requirements. 7.1.3 d/a analog output the csp1027 d/a has two analog outputs, aoutp and aoutn, capable of operating as two single-ended drivers, or a single fully differential driver. the output impedance of each is no more than 6 w (12 w if config- ured as fully differential) over the dc to 4 khz frequency range. the maximum open-circuit output levels are 2.1 vp (4.2 vp-p) if fully differential, and one-half of these lev- els if single-ended. these levels correspond to a full- scale 16-bit two's complement pcm input into the d/a converter, with the output gain setting (ogsel) at 0 db. for any given pcm input, the output levels will be reduced by a voltage division of the d/a output and the load impedance: the driver linearity is only guaranteed for the single- ended output load resistance (r l ) of at least 1000 w and the differential output load resistance (r l ) of at least 2000 w . rfb rin --------- - f lo 1 2 p rin cin -------------------------------------- - f hi 1 2 p rfb cfb --------------------------------------- == v out v o r l r o r l + --------------------- - =
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 34 7 application information (continued) figure 29 (ae) on page 35 illustrates five different analog output configurations. in figure 29a, the output load is driven in a fully differential manner. it is assumed that the load is floating, having no path to ground. figure 29b is similar, but ac-coupling capacitors are used. a low-pass pole is created, whose frequency should be less than 30 hz in order to not interfere with the voice band frequency response. in figure 29 (ce), different variations of single-ended loads are shown. in any single-ended configuration, ac- coupling capacitors are required. notes: analog (v ssa ) and digital (v ss ) ground pins are tied together to prevent substrate currents from ground bounce. capacitors c a2 , c d2 , c ref , c reg 1, and c reg 2 should be type x7r ceramic. capacitors c a1 and c d1 should be tantalum or low esr aluminum. all capacitors should be located as close to the chip pins as possible. keep analog and digital grounds separate, and then join at the v ssa pin. keep the regulator as close to the chip as possible. the power connections are shown when the analog and digital are run from 5.0 v. when the digital is run from a 3.3 v power supp ly, c d1 and c d2 go from the 3.3 v regulator to ground, and ra goes to the 5.0 v regulator. figure 28. analog external configurations in preamplifier mode (eigs = 0) 5-7607 (f) aoutp aoutn ro ro rl + C C + vo vo csp1027 v dd v ss to 5.0 v regulator v ss digital gnd plane v dda v ssa refc ra (3 w ) c a2 (0.1 m f) c a1 (10 m f) v ssa v ss v ssa c reg 2 (0.1 m f) analog gnd plane eigs auxin micin v reg c reg 1 (1 m f) v ssa cin (0.15 m f) c ref (0.22 m f) vin2 + microphone shielding C
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 35 7 application information (continued) figure 29. analog output configurations 5-7608 (f) aoutp aoutn aoutp aoutn aoutp aoutn cl cl rl rl rl rl nc vo ro e. dual single-ended c. single-ended, aoutp a. fully differential vo ro vo ro vo ro vo ro vo ro cl d. single-ended, aoutn b. fully differential, with capacitive coupling aoutp aoutn rl vo ro vo ro cl cl aoutp aoutn vo ro vo ro cl nc rl
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 36 7 application information (continued) 7.1.4 microphone regulator v reg is a 3.0 v regulated supply that provides up to 250 a to an external microphone or other device (see figure 28 on page 34). the regulator uses the external capacitors c reg 1 and c reg 2 to band limit its noise and for frequency compensation. the c reg 1 off-chip capacitor (1 f) is required in order to meet the noise specification of 100 v on v reg . c reg 2 (0.1 f) should be placed in parallel with c reg 1 to improve high-frequency noise filtering. the minimum value of the c reg 1 and c reg 2 combination is 0.1 f for v reg to be stable. if v reg is not used, this pin should be either connected through a 0.1 f capacitor to analog ground (v ssa ) or tied directly to ground. connecting v reg to ground will produce a dc current of 250 a to 400 a out the v reg pin, but will not change the total supply current. do not leave the v reg pin unconnected because it will oscillate. 7.2 power supply configuration figure 28 on page 34 illustrates the recommended configuration for the analog and digital power and grounds. an external supply feeds an off-chip voltage regulator. capacitor c d1 (10 f) and c d2 (0.1 f) are used for decoupling the noise on the v dd digital power bus. capacitors c a1 (10 f) and c a2 (0.1 f) are for de- coupling the noise on the analog power bus (v dda ). the ra resistor (3 w ) decouples the analog and digital power buses when a common 5.0 v power supply is used. the analog and digital circuits share the same substrate since this codec is a monolithic device. in the technology used to fabricate the device, the substrate is connected to ground. to avoid large substrate cur- rents caused by digital ground-bounce, it is recom- mended that the analog and digital grounds be tied together at the package, as shown in figure 28 on page 34. it is recommended that the analog and digital ground planes also meet at this point. in a typical appli- cation where the csp1027 is interfaced to a dsp, it is advisable to place the dsp as close to the codec as possible, with the dsp's digital ground plane extending to the points where the sio lines meet the csp1027. 7.2.1 refc capacitor an off-chip capacitor, c ref (0.22 f), is required on pin refc in order to meet the noise requirements for the internal signal paths. 7.2.2 capacitor proximity to pins in all cases, the external capacitors should be placed as closely as possible to the csp1027 pins, in order to meet the noise specifications. 7.3 the need for fully synchronous operation 7.3.1 introduction to sampled data systems the analog circuits in the a/d and d/a converters are sampled data circuits. this means that there are switches that close to sample the signal and then open to hold the signal. an example of this kind of discrete time analog circuit is the well-known switched capacitor technique used to implement a/d and d/a converter circuits as well as filters. a fundamental property of any sampled data system is that any noise or signal that is in the signal path when the sampling switches open is sampled. the sampling process modulates the noise and signal about multi- ples of the sample clock rate. for a sample rate of f s and a noise tone at a frequency of f n , this modulation process produces new tones at (k x f s ) f n , where k = 1, 2, 3 . . . . for noise near a multiple of f s , the difference term can modulate all the way down to baseband and be heard as a tone. a typical source of noise is that generated by the nor- mal operation of the digital circuits. the digital circuits tend to have fast edge transitions (large dv/dt and di/dt). the dv/dt changes couple into the analog signal path through parasitic capacitance on-chip and in the circuit board. the di/dt changes cause voltages to be generated across parasitic inductance and cause ground-bounce on-chip. the ground-bounce can turn on intrinsic parasitic diodes to the substrate of the csp1027, and the subsequent substrate currents can couple the noise into the analog circuits. the di/dt tran- sients are also inductively coupled into the off-chip analog routing and thus added to the analog signals. layout techniques help reduce the dv/dt and di/dt cou- pling, but it is very difficult to eliminate it. to gauge the magnitude of the problem, consider the numbers from the csp1027. the digital logic swing is ground to v dd , which can be as large as 5.5 v. the full-scale preamplifier input level (when irsel = 1) is 160 mvp, and the a/d path has a noise floor that is guaranteed to be 70 db below full scale. for the digital noise to raise the noise floor by less than 3 db, the
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 37 7 application information (continued) noise must be less than 36 vrms referred to the preamplifier input. as a worst-case analysis, assume that all the digital noise is in the baseband (noise source of 2.5 vrms for a 5.0 v digital signal). the atten- uation (isolation) between the digital signal and the preamplifier for this case must be isolation ? = 70,000:1 (97 db) usually, only a small portion of a particular digital signal ac-couples into the signal path, but this is tempered by having many digital signals. it is the sum of these noise sources that must be held to less than 36 vrms. in audio applications, the needed isolation is actually greater than calculated above because the human ear can detect tones that are 10 db below the noise floor. 7.3.2 typical ways digital noise couples into analog circuits 1. digital signals have overshoot or undershoot because of circuit board impedance mismatches. these reflections can turn on internal i/o protection diodes. the diodes then inject the noise current into the substrate as well as the chip power rails, and the noise is distributed throughout the chip. 2. fine-line cmos (like that used to fabricate the csp1027) generates hot electron currents when the logic gates change state. this current is injected into the substrate and adds to the supply current. the substrate current can couple directly into the analog circuits, and the supply current transients can couple through common supply impedance and by inductive coupling. 3. coupling off-chip, such as the package bond wires and package pins, and coupling into the analog sig- nals on the circuit board. 4. the classic coupling method: common power and ground impedance. 7.3.3 the problem with an asynchronous codec clock when the i/o and sample clocks are not derived from the same time base, their edges will drift with time. even if the i/o and sample time bases use master oscillators that are stated to be the same frequency (or one being a multiple of the other), they will differ by some amount from their intended values. this differ- ence in frequency will cause the digital circuit clock edges to slide past the analog sample clock edges in a periodic way, causing the sampled digital noise to also vary in the same periodic way (noise tones in the base- band). 7.3.4 the advantage of fully synchronous operation when all the clocks that are used in or connected to the codec are generated from the same master time base, the sampling switches sample in the quiet time before the digital circuits change state, or at least sample the same portion of the ground bounce transient. the por- tion of the noise that does not change from one sample to the next will alias to the signal path as a dc offset. the portion that is signal dependent (like a data line coupling into the analog signal path) can show up as a tone even though its transitions occur synchronously with the sample clock unless care is taken to ensure that the analog sampling switches only open during a quiet time (usually before the digital circuits change state). 2.5 v 36 m v ----------------
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 38 7 application information (continued) 7.4 crystal oscillator if the option for using the external crystal is chosen, the following electrical characteristics and requirements apply. 7.4.1 external components the crystal oscillator is enabled by connecting a crystal across xlo and xhi, along with one external capacitor from each of these pins to ground (see figure 30). for most applications, 10 pf external capacitors are recom- mended; however, larger values may be necessary if precise frequency tolerance is required (see section 7.4.5 on page 43). the crystal should be either fundamental or overtone mode, be parallel resonant, have a power dissipa- tion of at least 1 mw, and be specified at a load capacitance equal to the total capacitance seen by the crystal (including external capacitors and strays). the series resistance of the crystal should be specified to be less than half the absolute value of the negative resistance shown in figures 31 or 32 on page 39 for the crystal frequency. the frequency of the internal clock will be equal to the crystal frequency. figure 30. fundamental crystal configuration 7.4.2 power dissipation figures 33 and 34 on page 40 indicate the typical power dissipation of the on-chip crystal oscillator circuit versus frequency. xlo xhi xtal c 1 c 2 5-7609 (f)
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 39 7 application information (continued) figure 31. negative resistance of crystal oscillator circuit, v dd = 4.75 v figure 32. negative resistance of crystal oscillator circuit, v dd = 3.0 v 5-7610 (f) 0 C20 C40 C60 C80 C100 C120 C140 C200 5101520253035404550 frequency (mhz) re (z) ( w ) C160 C180 c ext = 50 pf xlo xhi c 1 c 2 c 0 z( w ) c 1 = c 2 = c ext proc 5.0 v 3.0 v 5.0 v 3.0 v 5.0 v 3.0 v c ext 10 pf 10 pf 20 pf 20 pf 50 pf 50 pf c 0 = parasitic capacitance of crystal (7 pf maximum) c ext = 10 pf c ext = 20 pf 5-7611 (f) 0 C20 C40 C60 C80 C100 C120 C140 C200 6 1014182226303438 frequency (mhz) re (z) ( w ) C160 C180 xlo xhi c 1 c 2 c 0 z( w ) c 1 = c 2 = c ext proc 5.0 v 3.0 v 5.0 v 3.0 v 5.0 v 3.0 v c ext 10 pf 10 pf 20 pf 20 pf 50 pf 50 pf 8 1216202428323640 c ext = 50 pf c 0 = parasitic capacitance of crystal (7 pf maximum) c ext = 10 pf c ext = 20 pf
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 40 7 application information (continued) figure 33. typical supply current of crystal oscillator circuit, v dd = 5.0 v, 25 c figure 34. typical supply current of crystal oscillator circuit, v dd = 3.3 v, 25 c 5-7612 (f) 6.5 6.0 5.5 5.0 4.5 3.0 2 8 14 18 22 26 30 34 38 frequency (mhz) average oscillator current (ma) 4.0 3.5 4 1216202428323640 10 6 7.0 c 1 = c 2 = 10 pf c 1 = c 2 = 50 pf 5-7613 (f) 1.5 0.0 2 8 14 18 22 26 30 frequency (mhz) average oscillator current (ma) 1.0 0.5 4 1216202428 10 6 2.0 0 c 1 = c 2 = 10 pf c 1 = c 2 = 50 pf
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 41 7 application information (continued) 7.4.3 printed-circuit board layout considerations the following guidelines should be followed when designing the printed-circuit board layout for a crystal-based application: 1. keep crystal and external capacitors as close to xlo and xhi pins as possible to minimize board stray capaci- tance. 2. keep high-frequency digital signals such as cko1 and cko2 away from xlo and xhi traces to avoid coupling into the oscillator. 7.4.4 lc network design for third overtone crystal circuits for operating frequencies of greater than 30 mhz, it is usually cost advantageous to use a third overtone crystal as opposed to a fundamental mode crystal. when using third overtone crystals, it is necessary, however, to filter out the fundamental frequency so that the circuit will oscillate only at the third overtone. there are several techniques that will accomplish this; one of these is described below. figure 35 shows the basic setup for third overtone operation. figure 35. third overtone crystal configuration the parallel combination of l 1 and c 1 forms a resonant circuit with a resonant frequency between the first and third harmonic of the crystal such that the lc network appears inductive at the fundamental frequency and capacitive at the third harmonic. this ensures that a 360 phase shift around the oscillator loop will occur at the third overtone frequency but not at the fundamental. the blocking capacitor, c 3 , provides dc isolation for the trap circuit and should be chosen to be large compared to c 1 . for example, suppose it is desired to operate with a 40 mhz, third overtone, crystal. let: f 3 = operating frequency of third overtone crystal (40 mhz in this example) f 1 = fundamental frequency of third overtone crystal, or f 3 /3 (13.3 mhz in this example) f t = resonant frequency of trap = c 2 = external load capacitor (10 pf in this example) c 3 = dc blocking capacitor (0.1 f in this example) xlo xhi xtal c 1 c 2 c 3 l 1 5-7614 (f) 1 2 p l1c1 --------------------------
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 42 7 application information (continued) arbitrarily set trap resonance to geometric mean of f 1 and f 3 . since f 1 = f 3 /3, the geometric mean would be: at the third overtone frequency, f 3 , it is desirable to have the net impedance of the trap circuit (x t ) equal to the impedance of c 2 (x c2 ), i.e., selecting c 3 so that x c3 << x l1 yields, for a capacitor, where w = 2 p f. for an inductor, solving for c 1 , and realizing that l 1 c 1 = 3/ w 3 2 yields, hence, for c 2 = 10 pf, c 1 = 15 pf. since the impedance of the trap circuit in this example would be equal to the impedance of a 10 pf capacitor, the negative resistance and supply current curves for c 1 = c 2 = 10 pf at 40 mhz would apply to this example. finally, solving for the inductor value, l 1 , for the above example, l 1 would be 3.2 m h. f t f 3 3 ------- 40 mhz 3 --------------------- - 23 mhz == = x t x c2 x c1 || x c3 x l1 + () == x t x c2 x c1 || x l1 == x c j C w c -------- = x l j w l = c 1 3 2 -- - c 2 = l 1 1 4 p 2 f 2 t c 2 --------------------------- - =
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 43 7 application information (continued) 7.4.5 frequency accuracy considerations for most applications, clock frequency errors in the hundreds of parts per million (ppm) can be tolerated with no adverse effect. however, for applications where precise frequency tolerance on the order 100 ppm is required, care must be taken in the choice of external components (crystal and capacitors) as well as in the layout of the printed- circuit board. several factors determine the frequency accuracy of a crystal-based oscillator circuit. some of these factors are determined by the properties of the crystal itself. generally, a low-cost, standard crystal will not be suffi- cient for a high-accuracy application, and a custom crystal must be specified. most crystal manufacturers provide extensive information concerning the accuracy of their crystals, and an applications engineer from the crystal ven- dor should be consulted prior to specifying a crystal for a given application. in addition to absolute, temperature, and aging tolerances of a crystal, the operating frequency of a crystal is also determined by the total load capacitance seen by the crystal. when ordering a crystal from a vendor, it is neces- sary to specify a load capacitance at which the operating frequency of the crystal will be measured. variations in this load capacitance due to temperature and manufacturing variations will cause variations in the operating fre- quency of the oscillator. figure 36 illustrates some of the sources of this variation. notes: c ext = external load capacitor (one each required for xlo and xhi). c d = parasitic capacitance of the csp1027 itself. c b = parasitic capacitance of the printed-wiring board. c 0 = parasitic capacitance of crystal (not part of c l , but still a source of frequency variation). figure 36. components of load capacitance for crystal oscillator the load capacitance, c l , must be specified to the crystal vendor. the crystal manufacturer will cut the crystal so that the frequency of oscillation will be correct when the crystal sees this load capacitance. note that c l refers to a capacitance seen across the crystal leads, meaning that for the circuit shown in figure 36, c l is the series combi- nation of the two external capacitors (c ext /2) plus the equivalent board and device strays (c b /2 + c d /2). for exam- ple, if 10 pf external capacitors were used and parasitic capacitance is neglected, then the crystal should be specified for a load capacitance of 5 pf. if the load capacitance deviates from this value due to the tolerance on the external capacitors or the presence of strays, then the frequency will also deviate. xlo xhi xtal c d c b c ext c d c b c ext c l c o 5-7615 (f)
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 44 7 application information (continued) this change in frequency as function of load capacitance is known as pullability and is expressed in units of ppm/ pf. for small deviations of a few pf, pullability can be determined by the equation below. pullability (ppm/pf) = where c 0 = parasitic capacitance of crystal. c 1 = motional capacitance of crystal (usually around 1 ff25 ff, value can be obtained from crystal vendor). c l = total load capacitance seen by crystal. note that for a given crystal, the pullability can be reduced, and hence, the frequency stability improved, by making c l as large as possible while still maintaining sufficient negative resistance to ensure start-up per the curves shown in figures 31 and 32 on page 39. since it is not possible to know the exact values of the parasitic capacitance in a crystal-based oscillator system, the external capacitors are usually selected empirically to null out the frequency offset on a typical prototype board. thus, if a crystal is specified to operate with a load capacitance of 10 pf, the external capacitors would have to be made slightly less than 20 pf each in order to account for strays. suppose, for instance, that a crystal for which c l = 10 pf is specified is plugged into the system and it is determined empirically that the best frequency accuracy occurs with c ext = 18 pf. this would mean that the equivalent board and device strays from each lead to ground would be 2 pf. as an example, suppose it is desired to design a 26 mhz, 3.3 v system with 100 ppm frequency accuracy. the parameters for a typical high-accuracy, custom, 26 mhz fundamental mode crystal are as follows: initial tolerance 10 ppm temperature tolerance 25 ppm aging tolerance 6 ppm series resistance 20 w max motional capacitance (c 1 ) 15 pf max parasitic capacitance (c 0 ) 7 pf max in order to ensure oscillator start-up, the negative resistance of the oscillator with load and parasitic capacitance must be at least twice the series resistance of the crystal, or 40 w . interpolating from figure 32 on page 39, exter- nal capacitors plus strays can be made as large as 30 pf while still achieving 40 w of negative resistance. assume for this example that external capacitors are chosen so that the total load capacitance including strays is 30 pf per lead, or 15 pf total. thus, a load capacitance, c l = 15 pf would be specified to the crystal manufacturer. from the above equation, the pullability would be calculated as follows: pullability = = = 15.5 ppm/pf if 2% external capacitors are used, the frequency deviation due to this variation is equal to (0.02)(15 pf)(15.5 ppm/pf) = 4.7 ppm. note: to simplify analysis, c ext is considered to be 30 pf. in practice, it would be slightly less than this value to account for strays. also, temperature and aging tolerance on the capacitors have been neglected. typical capacitance variation of oscillator circuit in the csp1027 itself across process, temperature, and supply voltage is 1 pf. thus, the expected frequency variation due to the csp1027 is as follows: (1 pf)(15.5 ppm/pf) = 15.5 ppm. approximate variation in parasitic capacitance of crystal = 0.5 pf. frequency shift due to variation in c 0 = (0.5 pf)(15.5 ppm/pf) = 7.75 ppm. approximate variation in parasitic capacitance of printed-circuit board = 1.5 pf. frequency shift due to variation in board capacitance = (1.5 pf)(15.5 ppm/pf) = 23.25 ppm. c 1 () 10 6 () 2c 0 c l + () 2 ------------------------------- - c 1 () 10 6 () 2c 0 c l + () 2 ------------------------------- 0.015 () 10 6 () 27 15 + () 2 ----------------------------------
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 45 7 application information (continued) thus, the contributions to frequency variation add up as follows: initial tolerance of crystal 10.0 ppm temperature tolerance of crystal 25.0 ppm aging tolerance of crystal 6.0 ppm load capacitor variation 4.7 ppm csp1027 circuit variation 15.5 ppm c 0 variation 7.8 ppm board variation 23.3 ppm total 92.3 ppm this type of detailed analysis should be performed for any crystal-based application where frequency accu- racy is critical. 7.5 programmable clock generation refer to figure 17 on page 15 for the following discus- sion. the programmable clock divider is set by writing the 6-bit cdiv3 field of the cioc2 register (see table 9 on page 28). the user can select an appropriate integer value which sets the ratio of the clk input clock to the oversampling rate of the codec. the following examples illustrate this feature. 7.5.1 application example 1 n gsm application. n input clock, clk, rate: 26 mhz (38.46 ns). n codec pcm rate required: 8 khz (oversampling rate = 1 mhz). solution: n clk/ck os = 26, so set clk/iclk0 = 1 and iclk0/ ck os to 26. n set cdiv0 = 0 and cdiv3 = 26 (011010). 7.5.2 application example 2 n is-54 application. n input clock, clk, rate: 40 mhz (25.0 ns). n codec pcm rate required: 8 khz (oversampling rate = 1 mhz). solution: n clk/ck os = 40, so set clk/iclk0 = 1 and iclk0/ ck os to 40. n set cdiv0 = 0 and cdiv3 = 40 (101000). 7.5.3 application example 3 n modem data pump. n codec sampling frequency required = 9.6 khz (instead of 8 khz). n need highest possible input clock, clk, rate (allow- able by the dsp). solution: n codec oversampling rate = 9.6 khz * 125 = 1.2 mhz. n assuming a dsp16a or dsp1616 with maximum rate of 40 mhz, clk = 39.6 mhz = 1.2 mhz x 33, so clk/iclk0 = 1 and iclk0/ck os = 33. n set cdiv0 = 0 and cdiv3 = 33 (100001). n disable the high-pass filters (hpfe = 1) because the C3 db corner frequency is now too high (270 hz x 1.2 = 324 hz). n low-pass filter C3 db corner frequency is now 4.08 khz (= 3.4 khz x 1.2). (note that external dsp software can provide additional postfiltering, if desired.)
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 46 7 application information (continued) 7.5.4 enhanced oversampling clock generation if system constraints make the requirement of integer multiples of 125 x the sampling rate (typically integer multiples of 1.0 mhz) difficult to provide, the csp1027 can also operate with the iclk0 internal clock rate at integer multiples of the sampling rate (typically integer multiples of 8 khz). see section 4.5 on page 16 for more information. the following two examples illustrate the usage: application example 4 n standard codec application. n clk input clock rate: 2.048 mhz. n codec sampling rate, f s : 8 khz. solution: n ck os = 125 x 8 khz = 1.0 mhz, so clk/ck os = 2.048 or clk/ck s = 2.048 x 125 = 256. values of m and n must be found to satisfy this requirement, as shown below. n set cdiv0 for 1 (cdiv0 = 0); hence, f iclk = f clk. n using the equations from section 4.5 on page 16, hence, m = 2, s = 1, and n = 6. (note that if cdiv0 set for 2, then m = 1, s = +1, and n = 3, which is not allowed.) n using tables 2 through 4 on page 18: cdiv3 = 00 0010. cdifs = 0. cdif0 = 01 0101. cdif1 = 10 0110. cdif2 = 0 0000. application example 5 n is-54 application. n codec sampling rate, f s : 8 khz. n clk needs to be a common multiple of 8 khz and 48 x 48.6 khz. n need phase adjustment. solution: n 48 x 48.6 = 2.3328e6 2.3328e6 8e3 = 291.6 to get a common multiple, 291.6 must be multiplied by a factor to become an integer: 291.6 x 10 = 2916 (an integer). so, clk/ck s = 2916 and clk/iclk0 = 2 clk = 2916 x 8e3 = 23.328e6. n clk input clock rate: 23.328 mhz. n set cdiv0 for 2 (cdiv0 = 1) to allow advance/ retard for phase adjustment. n iclk0 internal clock rate is 11.664 mhz. n using the equations from section 4.5 on page 16, hence, m = 12, s = C1, and n = 42. n using tables 2 through 4 on page 18: cdiv3 = 00 1100. cdifs = 1. cdif0 = 00 0011. cdif1 = 11 0110. cdif2 = 0 0000. f iclk0 f s ---------------- - 125 m () s2 () + = f iclk0 f s ---------------- - 2.048 mhz 8 khz ----------------------------- - 256 125 2 () 16 () + === f iclk0 f s ---------------- - 11.664 mhz 8 khz --------------------------------- 1458 125 12 () 1 C 42 () + ===
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 47 8 device characteristics 8.1 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. external leads can be bonded and soldered safely at temperatures of up to 300 c. voltage range on any pin with respect to ground................................................................. C0.5 v to +6 v power dissipation .............................................................................................................. ................... 0.3 w ambient temperature range...............................................................................................C40 c to +85 c storage temperature range ....................................................................................................... C 65 c to +150 c 8.2 handling precautions all mos devices must be handled with certain precautions to avoid damage due to the accumulation of static charge. although input protection circuitry has been incorporated into the devices to minimize the effect of this static buildup, proper precautions should be taken to avoid exposure to electrostatic discharge during handling and mounting. agere employs a human-body model for esd-susceptibility testing. since the failure voltage of electronic devices is dependent on the current, voltage, and, hence, the resistance and capacitance, it is important that stan- dard values be employed to establish a reference by which to compare test data. values of 100 pf and 1500 w are the most common and are the values used in the agere human-body model test circuit. the breakdown voltage for the csp1027 is greater than 1000 v. 8.3 recommended operating conditions 8.3.1 package thermal considerations the recommended operating temperature specified above is based on the maximum power, package type, and maximum junction temperature. the following equation describes the relationship between these parameters. cer- tain applications' maximum power may be less than the worst-case value and can use this relationship to determine the maximum ambient temperature allowed. t a = t j C p x q ja maximum junction temperature (t j ) in 44-pin qfp ...........................................................................125 c 44-pin qfp maximum thermal resistance in still-air-ambient ( q ja ).............................................. 39 c/w maximum junction temperature (t j ) in 48-pin tqfp.........................................................................125 c 48-pin tqfp maximum thermal resistance in still-air-ambient ( q ja ) ........................................... 90 c/w table 11. recommended operating conditions parameter symbol min max unit analog supply voltage v dda 4.5 5.5 v digital supply voltage v dd 2.7 5.5 v ambient temperature t a C40 85 c
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 48 9 electrical characteristics and requirements the following electrical characteristics are preliminary and are subject to change. electrical characteristics refer to the behavior of the device under specified conditions. electrical requirements refer to conditions imposed on the user for proper operation of the device. the parameters below are valid for the following conditions: v dd = 5 v 10% (see section 8.3 on page 47 for exceptions.) table 12. digital electrical characteristics and requirements parameter symbol min max unit input voltage (except porcap): low high v il v ih 0.7 x v dd 0.3 x v dd v v porcap input voltage: low high v il v ih 0.7 x v dd 0.5 x v dd v v input current (except eigs, iock, porcap): low (v il = 0 v) high (v ih = 5.5 v) i il i ih C5 5 a a input current (eigs): low (v il = 0 v) high (v ih = 5.5 v) i il i ih C5 100 a a input current (iock): low (v il = 0 v) high (v ih = 5.5 v) i il i ih C100 5 a a input current (porcap): low (v il = 0 v) high (v ih = 5.5 v) i il i ih C100 5 a a output low voltage: low (i ol = 2.0 ma) low (i ol = 50 a) v ol v ol 0.4 0.2 v v output high voltage: high (i oh = C2.0 ma) high (i oh = C50 a) v oh v oh v dd C 0.7 v dd C 0.2 v v output 3-state current: low (v dd = 5.5 v, v il = 0 v) high (v dd = 5.5 v, v ih = 5.5 v) i ozl i ozh C10 10 a a input capacitance c i 10 pf
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 49 9 electrical characteristics and requirements (continued) figure 37. plot of v oh vs. i oh under typical operating conditions figure 38. plot of v ol vs. i ol under typical operating conditions 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 i oh (ma) v oh (v) device under test v oh i oh 5-7616 (f) 5-7617 (f) 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 i ol (ma) v ol (v) device under test v ol i ol 0.10 0.05
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 50 9 electrical characteristics and requirements (continued) 9.1 power dissipation power dissipation is highly dependent on the frequency of operation. the typical power dissipation listed is for a selected application. the following electrical characteristics are preliminary and are subject to change. the power dissipation listed is for internal power dissipation only. total power dissipation can be calculated on the basis of the application by adding c x v dd 2 x f for each output, where c is the additional load capacitance and f is the effective output frequency. power dissipation due to the input and i/o buffers is highly dependent on the input voltage level. at full cmos lev- els, essentially no dc current is drawn. however, for levels near the threshold of 0.5 x v dd , high and unstable levels can flow. therefore, all unused input pins should be tied inactive to v dd or v ss , and all unused i/o pins should be tied inactive through a 10 k w resistor to v dd or v ss . table 13 shows the input buffer power dissipation for inputs at dc levels, v dd or v ss . table 13. power dissipation operating mode analog supply (v dda ) digital supply (v dd ) 5.0 v 5.0 v 3.3 v 3.0 v typ 5.0 v max 5.5 v typ 5.0 v max 5.5 v typ 3.3 v max 3.6 v typ 3.0 v max 3.3 v codec active, crystal osc. disabled ( cioc0 : active = 1, xoscen = 0, clk at 25 mhz, iock at 6.25 mhz, ck os at 1 mhz) 11.0 ma 55.0 mw 12.2 ma 67.1 mw 4.6 ma 23.0 mw 5.8 ma 31.9 mw 3.0 ma 9.9 mw 3.8 ma 13.7 mw 2.8 ma 8.4 mw 3.5 ma 11.5 mw codec inactive, crystal osc. disabled ( cioc0 : active = 0, xoscen = 0, clk at 25 mhz, iock at 6.25 mhz) 0.01 ma 0.05 mw 0.02 ma 0.11 mw 3.7 ma 18.5 mw 4.9 ma 26.9 mw 2.5 ma 8.2 mw 3.2 ma 11.5 mw 2.2 ma 6.6 mw 2.9 ma 9.6 mw codec active, crystal osc. enabled ( cioc0 : active = 1, xoscen = 1, 25 mhz crystal, iock at 6.25 mhz, ck os at 1 mhz) 11.0 ma 55.0 mw 12.2 ma 67.1 mw 10.2 ma 51.0 mw 11.4 ma 62.7 mw 4.1 ma 13.5 mw 5.0 ma 18.0 mw 3.9 ma 11.7 mw 4.7 ma 15.5 mw codec inactive, crystal osc. enabled ( cioc0 : active = 0, xoscen = 1, 25 mhz crystal, iock at 6.25 mhz) 0.01 ma 0.05 mw 0.02 ma 0.11 mw 9.3 ma 46.5 mw 10.5 ma 57.8 mw 3.6 ma 11.9 mw 4.4 ma 15.8 mw 3.3 ma 9.9 mw 4.1 ma 13.5 mw
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 51 10 analog characteristics and requirements the following analog characteristics and requirements are preliminary information and are subject to change. ana- log characteristics refer to the behavior of the device under specified conditions. analog requirements refer to con- ditions imposed on the user for proper operation of the device. all analog data is valid for the following conditions unless otherwise specified: n t a = C40 c to +85 c. n v dda = 5 v 10% (see section 8.2 on page 47.) n sampling frequency = 8 khz, oversampling clock (ck os ) = 1.0 mhz, input clock (clk) = 25 mhz. n 0.22 f capacitors connected to the refc pin. n 0.15 f coupling capacitors connected to the micin and auxin pins when eigs = 0. n rfb = rin = 24 k w , cfb = 270 pf, and cin = 1 f when in the external input gain select mode (eigs = 1). n 2 k w differential output load connected between aoutp and aoutn pins. n 1 f and 0.1 f bypass capacitors connected between the v reg and v ssa . n 0 dbm0 is the level that corresponds to a sine wave that is 3.14 db below the clipping (overload) level at the out- put of the a/d or input to the d/a. n all noise and distortion measurements are flat weighted and integrated over the 300 hz to 4 khz frequency band. 10.1 analog input and microphone regulator note: the input clipping level corresponds to an a/d path output of 3.14 dbm0. note: v reg must be bypassed to analog ground through a 1 f low esr capacitor to meet this noise specification. the minimum bypass capac- itance for stable v reg operation is 0.1 f, with a maximum noise of 200 vrms. table 14. analog input characteristics and requirements symbol parameter min typ max unit rin a/d input resistance of auxin and micin: eigs = 0 eigs = 1 40 1000 k w k w cin a/d input capacitance on auxin and micin 20 pf a/d input clipping level at auxin or micin: eigs = 0, cioc0 : irsel = 0 eigs = 0, cioc0 : irsel = 1 0.490 0.143 0.500 0.160 0.510 0.180 vp vp a/d input clipping level at auxin: eigs = 1 1.49 1.578 1.67 vp gain referred to nominal clipping level: eigs = 0, cioc0 : irsel = 0 eigs = 0, cioc0 : irsel = 1 eigs = 1 C0.18 C1.0 C0.5 0 0 0 0.18 1.0 0.5 db db db table 15. microphone regulator characteristics parameter min typ max unit v reg output voltage 2.7 3.0 3.3 vrms v reg output current 250 a v reg output noise 100 vrms
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 52 10 analog characteristics and requirements (continued) 10.2 analog-to-digital path notes: the signal to distortion plus noise ratio is from the micin or auxin input to the pcm output when eigs = 0, and from vin (of fi gure 5 on page 7) to pcm output when eigs = 1. the a/d signal to distortion plus noise ratio is valid for sampling rates up to 16 khz. for sampling rates between 16 khz and 2 4 khz, the signal to distortion plus noise ratio is no better than 60 db. * gain is relative to the 0 dbm0 signal level with eigs = 0 and irsel = 0. note: the frequency response scales linearly with codec oversampling clock rate. frequencies greater than 4000 hz are affected b y antialias filtering attenuation. table 16. a/d signal to distortion plus noise ratio output signal level preamp (eigs = 0) 0.5 vp range (cioc0: irsel = 0) preamp (eigs = 0) 0.16 vp range (cioc0: irsel = 1) ext. gain select (eigs = 1) 1.578 vp range unit min max min max min max 0 dbm0 71 68 71 db C10 dbm0 62 59 62 db C30 dbm0 42 39 42 db C40 dbm0 32 29 32 db C45 dbm0 27 24 27 db C55 dbm0 17 14 17 db table 17. a/d relative gain accuracy * output signal level min max unit +3 dbm0 to C40 dbm0 C0.1 0.1 db C40 dbm0 to C50 dbm0 C0.4 0.4 db C50 dbm0 to C55 dbm0 C1.2 1.2 db table 18. a/d frequency response relative to 1 khz output level (f os = 1 mhz and f s = 8 khz) frequency high-pass filter enabled (hpfe = 0) high-pass filter disabled (hpfe = 1) unit min max min max 50 hz C40 C0.25 0.25 db 60 hz C40 C0.25 0.25 db 100 hz C34 C18 C0.25 0.25 db 200 hz C12 0 C0.25 0.25 db 300 hz C0.25 0.25 C0.25 0.25 db 3000 hz C0.25 0.25 C0.4 0.25 db 3400 hz C0.9 0.25 C0.9 0.25 db 4000 hz C6 C6 db 4600 hz C35 C35 db 8000 hz C45 C45 db
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 53 10 analog characteristics and requirements (continued) 10.3 digital-to-analog path notes: the d/a signal to distortion plus noise ratio decreases by 3 db for each 3 db gain step below 0 db. the d/a sdnr is specified w ith a differential load. for a single-ended load, the d/a sdnr is degraded by about 6 db. the d/a signal to distortion plus noise ratio is valid for sampling rates up to 16 khz. for sampling rates between 16 khz and 2 4 khz, the signal to distortion plus noise ratio is no better than 60 db. table 19. d/a signal to distortion plus noise ratio (0 db output setting) output signal level min max unit 0 dbm0 72 db C10 dbm0 62 db C30 dbm0 42 db C40 dbm0 32 db C45 dbm0 27 db C55 dbm0 17 db table 20. d/a relative gain accuracy* * gain is relative to the 0 dbm0 signal level. absolute gain accuracy at the 0 dbm0 signal level is 0.18 db. digital-to-analog path gain is spec- ified with a differential load; a single-ended load adds 0.1 db to absolute gain. output signal level min max unit +3 dbm0 to C40 dbm0 C0.1 0.1 db C40 dbm0 to C50 dbm0 C0.4 0.4 db C50 dbm0 to C55 dbm0 C1.2 1.2 db table 21. d/a output gain adjustment gain setting min typ max unit 0 db C0.2 0 0.2 db C3 db C3.21 C3.01 C2.81 db C6 db C6.22 C6.02 C5.82 db C9 db C9.23 C9.03 C8.83 db C12 db C12.24 C12.04 C11.84 db . . . . . . . . . . . . . . . C42 db C42.34 C42.14 C41.94 db C45 db C45.35 C45.15 C44.95 db
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 54 10 analog characteristics and requirements (continued) 10.4 miscellaneous * the codec is intended to drive a floating 2 k w load, such as a telephone handset speaker, or 1 k w loads ac-coupled to ground on both ana- log outputs. since the codec outputs aoutp and aoutn have common-mode dc voltage, ac coupling must be used if there is a dc pat h to v dd or v ss (ground) through the load. table 22. d/a frequency response relative to 1 khz output level (f os = 1 mhz and f s = 8 khz) frequency high-pass filter enabled (hpfe = 0) high-pass filter disabled (hpfe = 1) unit min max min max 50 hz C40 C0.25 0.25 db 60 hz C40 C0.25 0.25 db 100 hz C34 C18 C0.25 0.25 db 200 hz C12 0 C0.25 0.25 db 300 hz C0.25 0.25 C0.25 0.25 db 3000 hz C0.25 0.25 C0.25 0.25 db 3400 hz C0.9 0.25 C0.9 0.25 db 4000 hz C6 C6 db 4600 hz C35 C35 db 8000 hz C45 C45 db table 23. other analog characteristics and requirements* parameter min max unit d/a differential output resistance (0 khz to 4 khz) 12 w d/a single-ended output resistance (0 khz to 4 khz) 6 w analog-to-digital power supply rejection ratio at 3 khz 30 db digital-to-analog power supply rejection ratio at 3 khz 40 db analog input coupling capacitor input leakage current 30 na idle channel noise at analog-to-digital output with input gain setting of 500 mvp or 160 mvp C65 dbm0 idle channel noise at digital-to-analog output 300 vrms a/d to d/a and d/a to a/d crosstalk C65 db digital-to-analog image frequency attenuation above 4600 hz 35 db digital-to-analog output amplifier differential swing for 2 k w load 1.5 vrms codec filter group delay for frequencies less than 800 hz 2.8 ms codec filter group delay for frequencies greater than 800 hz 0.8 ms recovery time of digital-to-analog output due to a change from inac- tive mode to active mode, muted to not muted, or change in output gain (see cioc0 register, active, mute, ogsel.) 100 ms recovery time of analog-to-digital pcm output and v reg due to a change from inactive mode to active mode (see cioc0 register, active.) 600 ms recovery time of analog circuits due to a change in input select or input range (see cioc0 register, insel and irsel.) 100 ms allowable clk input jitter C5 5 ns allowable clk frequency error C1 1 %
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 55 11 timing characteristics and requirements the following timing characteristics and requirements are preliminary information and are subject to change. tim- ing characteristics refer to the behavior of the device under specified conditions. timing requirements refer to con- ditions imposed on the user for proper operation of the device. all timing data is valid for the following conditions: t a = C40 c to +85 c or 0 c to 70 c (see section 8.2 on page 47.) v dd = 5 v 0.5 v, 3.3 v 0.3 v, or 3.0 v 0.3 v, v ss = 0 v (see section 8.2 on page 47.) capacitance load on outputs (c l ) = 50 pf output characteristics can be derated as a function of load capacitance (c l ). all outputs: dt/dc l 0.06 ns/pf for 0 c l 100 pf at v ih for rising edge dt/dc l 0.05 ns/pf for 0 c l 100 pf at v il for falling edge for example, if the actual load capacitance is 30 pf instead of 50 pf, the derating for a rising edge is (30 pf C 50 pf) x 0.06 ns/pf = 1.2 ns less than the specified rise time or delay which includes a rise time. test conditions for inputs: n rise and fall times of 4 ns or less n timing reference levels for delays = v ih , v il test conditions for outputs: n c load = 50 pf n timing reference levels for delays = v ih , v il n 3-state delays measured to the high-impedance state of the output driver
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 56 11 timing characteristics and requirements (continued) 11.1 clock generation * oscen = 0 shown. ? cdiv0 = 2, cdiv1 = 1 configuration shown (see table 8 on page 27). ? cdiv2 = 4 option shown (see table 8 on page 27). figure 39. clock timing diagram * device is fully static, t1 is tested at 500 ns. table 24. timing requirements for input clock abbreviated reference parameter 5.0 v 3.3 v 3.0 v unit min max min max min max t1 clock in period (high to high) 25 * 42 * 60 * ns t2 clock in low time (low to change) 11 19 27 ns t3 clock in high time (high to change) 11 19 27 ns table 25. timing characteristics for output clocks abbreviated reference parameter 5.0 v 3.3 v 3.0 v unit min max min max min max t7 clock out 1 delay (valid to valid) 30 54 66 ns t8 clock out 2 delay (valid to valid) 20 40 50 ns clk * v ihC v ilC t1 t3 t2 t7 t8 cko1 ? v ohC v olC cko2 ? v ohC v olC 5-7618 (f)
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 57 11 timing characteristics and requirements (continued) 11.2 power-on reset the csp1027 has a power-on reset circuit that automatically clears the device upon power-on. if the supply voltage falls below v dd min * , the device must be reset. figure 40 on page 57 shows two separate events: an initial power- on and a power-on following a drop in the power supply. * see table 11 on page 47. figure 40. power-on reset timing diagram note: the device needs to be clocked for at least six clk cycles during reset after power-on. otherwise, high and unstable curre nt may flow. table 26. timing requirement for power-on reset abbreviated reference parameter min max unit t9 v dd ramp 1 ms table 27. timing characteristic for power-on reset abbreviated reference parameter min max unit t10 porb pulse width (low to change) 1.5 7 ms v dd ramp porb v oh v ol 0 v v dd min t10 t10 v dd min 0.5 v t9 t9 5-7619 (f)
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 58 11 timing characteristics and requirements (continued) 11.3 reset note: cko1 and cko2 are active during reset and synchronized by the rising edge of reset. figure 41. reset timing table 28. timing requirements for reset timing abbreviated reference parameter min max unit t4 reset hold (high to change) 2 ns t5 reset setup (valid to high) 4 ns t6 reset pulse (low to high) 6t ns clk v ihC v ilC rstb v ihC v ilC cko1 v ohC v olC cko2 v ohC v olC t6 t4 t5 5-7620 (f)
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 59 11 timing characteristics and requirements (continued) 11.4 serial i/o communication figure 42. serial input/output timing diagram table 29. timing requirements for serial input/output abbreviated reference parameter 5.0 v 3.3 v 3.0 v unit min max min max min max t11 clock period (high to high) 50 * * device is fully static; t11 is tested at 100 ns. the frequency of iock must be greater than the frequency of the internal over sampling clock ckos (f ckos ). 84 * 120 * ns t12 clock low time (low to change) 20 33 48 ns t13 clock high time (high to change) 20 33 48 ns t14 sync high setup (high to high) 6 11 13 ns t15 sync low setup (low to high) 9 15 20 ns t16 sync hold (high to invalid) 0 0 0 ns t17 data setup (valid to high) 6 11 13 ns t18 data hold (high to invalid) 0 0 0 ns t19 address setup (valid to high) 9 15 20 ns t20 address hold (high to invalid) 0 0 0 ns table 30. timing characteristics for serial input/output abbreviated reference parameter 5.0 v 3.3 v 3.0 v unit min max min max min max t21 data/status delay (high to valid) 26 50 57 ns t22 data/status hold (high to invalid) 2 2 2 ns t11 t13 t12 t14 t16 t15 t16 t17 t18 t19 t20 t21 t22 t22 t20 t18 sync v ihC v ilC di v ihC v ilC sadd v ihC v ilC do v ohC v olC iock v ihC v ilC b15 b14 b8 b0 ad0 ad1 as0 as7 b15 b14 b8 b0 5-7621 (f)
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 60 11 timing characteristics and requirements (continued) figure 43. serial i/o active mode timing diagram table 31. timing characteristics for active mode abbreviated reference parameter 5.0 v 3.3 v 3.0 v unit min max min max min max t23 sync delay (high to valid) 26 50 55 ns t24 sync hold (high to invalid) 2 2 2 ns t24 t23 t24 t23 iock v ohC v olC sync v ohC v olC 5-7622 (f)
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 61 11 timing characteristics and requirements (continued) 11.5 serial multiprocessor communication figure 44. sio multiprocessor timing diagram note: capacitance load on do, sync, and sadd = 100 pf. table 32. timing requirements for multiprocessor communication abbreviated reference parameter 5.0 v 3.3 v 3.0 v unit min max min max min max t25 sync high setup (high to high) 10 16 23 ns t26 sync low setup (low to high) 22 35 44 ns t27 sync hold (high to invalid) 2 0 0 ns table 33. timing characteristics for multiprocessor communication abbreviated reference parameter 5.0 v 3.3 v 3.0 v unit min max min max min max t28 data delay (bit 0 only) (low to valid) 24 48 55 ns t29 data disable delay (high to 3-state) 18 26 35 ns t30 address delay (bit 0 only) (low to valid) 26 50 57 ns t31 address delay (high to valid) 22 40 48 ns t32 address hold (low to valid) 2 2 2 ns t33 address disable delay (high to 3-state) 18 28 35 ns b15 b14 b8 b7 b0 b15 b0 ad0 ad1 ad7 as0 ad0 as7 iock sync v ihC v ilC do/di v ohC v olC sadd t27 t26 t27 t25 t28 t31 t30 t32 t33 t29 5-7623 (f)
csp1027 voice band codec for data sheet cellular handset and modem applications january 2002 agere systems inc. 62 12 outline diagrams 12.1 44-pin eiaj quad flat pack (qfp) controlling dimensions are in millimeters. note: the production line has been qualified at agere-sgp for this outline; also second-source (shinko) tolerances have been acc ommodated on the above diagram. 44 1 10.00 0.20 13.20 0.20 10.00 0.20 13.20 0.20 pin #1 identifier zone 11 12 22 23 33 34 0.80 typ detail a 2.35 max 0.10 seating plane 1.95/2.10 detail b 0.25 max 0.30/0.45 0.20 m 0.130/0.230 detail b 0.25 0.73/1.03 1.60 ref gage plane seating plane detail a 5-2111 (f) r.12
agere systems inc. data sheet csp1027 voice band codec for january 2002 cellular handset and modem applications 63 12 outline diagrams (continued) 12.2 48-pin eiaj thin quad flat pack (tqfp) controlling dimensions are in millimeters. note: the above outline fully meets jedec standard mo-136 dated april 1993. pin #1 identifier zone 24 7.00 0.20 1 48 37 12 13 36 25 9.00 0.20 7.00 0.20 1.60 max seating plane detail a 0.08 1.40 0.05 0.50 typ 0.05/0.15 detail b 9.00 0.20 detail b 0.19/0.27 0.08 m 0.106/0.200 detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25 5-2363 (f) r.8
agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. copyright ? 2002 agere systems inc. all rights reserved january 2002 ds02-058auto (replaces ds00-063auto) for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com e-mail: docmaster@agere.com n. america: agere systems inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-5047-1212 (shanghai), (86) 10-6522-5566 (beijing), (86) 755-695-7224 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 7000 624624 , fax (44) 1344 488 045

▲Up To Search▲

Price & Availability of CPS1027-S

	To Download CPS1027-S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .